SBAS614C May   2013  – March 2019 ADS8866


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      No Separate LDO Required for the ADC Supply
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements: 3-Wire Operation
    7. 7.7 Timing Requirements: 4-Wire Operation
    8. 7.8 Timing Requirements: Daisy-Chain
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
    1. 8.1 Equivalent Circuits
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog Input
      2. 9.3.2 Reference
      3. 9.3.3 Clock
      4. 9.3.4 ADC Transfer Function
    4. 9.4 Device Functional Modes
      1. 9.4.1 CS Mode
        1. 3-Wire CS Mode
        2. 4-Wire CS Mode
      2. 9.4.2 Daisy-Chain Mode
        1. Daisy-Chain Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 ADC Reference Driver
      2. 10.1.2 ADC Input Driver
        1. Input Amplifier Selection
        2. Charge-Kickback Filter
    2. 10.2 Typical Applications
      1. 10.2.1 DAQ Circuit for a 10-µs, Full-Scale Step Response
        1. Design Requirements
        2. Detailed Design Procedure
      2. 10.2.2 DAQ Circuit for Lowest Distortion and Noise Performance at 100 kSPS
        1. Design Requirements
        2. Detailed Design Procedure
      3. 10.2.3 Ultralow-Power DAQ Circuit at 10 kSPS
        1. Design Requirements
        2. Detailed Design Procedure
  11. 11Power Supply Recommendations
    1. 11.1 Power-Supply Decoupling
    2. 11.2 Power Saving
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

Figure 58 shows a board layout example for the device. Appropriate layout that interconnects accompanying capacitors and converters with low inductance is critical for achieving optimum performance. Thus, a PCB board with at least four layers is recommended to keep all critical components on the top layer and interconnected to a solid (low inductance) analog ground plane at the subsequent inner layer using 15-mil vias. Avoid crossing digital lines with the analog signal path and keep the analog input signals and the reference input signals away from noise sources. As shown in Figure 58, the analog input and reference signals are routed on the left side of the board and the digital connections are routed on the right side of the device.

As a result of dynamic currents during conversion and data transfer, each supply pin (AVDD and DVDD) must have a decoupling capacitor to keep the supply voltage stable. To maximize decoupling capabilities, inductance between each supply capacitor and the supply pin of the converter is kept less than 5 nH by placing the capacitor within 0.2-inches from the pin and connecting it with 20-mil traces and a 15-mil grounding via, as shown in Figure 58. TI recommends using one 1-μF ceramic capacitor at each supply pin. Avoid placing vias between the supply pin and its decoupling capacitor.

Dynamic currents are also present at the REF pin during the conversion phase and very good decoupling is critical to achieve optimum performance. The inductance between the reference capacitor and the REF pin is kept less than 2 nH by placing the capacitor within 0.1-inches from the pin and connecting it with 20-mil traces and multiple 15-mil grounding vias, as shown in Figure 58. A single, 10-μF, X7R-grade, 0805-size, ceramic capacitor with at least a 10-V rating is recommended for good performance over the rated temperature range. Avoid using additional lower value capacitors because the interactions between multiple capacitors may affect the ADC performance at higher sampling rates. A small, 0.1-Ω to 0.47-Ω, 0603-size resistor placed in series with the reference capacitor (as shown in Figure 58) keeps the overall impedance low and constant, especially at very high frequencies.

The fly-wheel RC filters are placed immediately next to the input pins. Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.