SBAS729C June   2016  – August 2026 ADS8920B , ADS8922B , ADS8924B

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 LDO Module
      2. 6.3.2 Reference Buffer Module
      3. 6.3.3 Converter Module
        1. 6.3.3.1 Sample-and-Hold Circuit
        2. 6.3.3.2 Internal Oscillator
        3. 6.3.3.3 ADC Transfer Function
      4. 6.3.4 Interface Module
    4. 6.4 Device Functional Modes
      1. 6.4.1 RST State
      2. 6.4.2 ACQ State
      3. 6.4.3 CNV State
    5. 6.5 Programming
      1. 6.5.1 Output Data Word
      2. 6.5.2 Data Transfer Frame
      3. 6.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 6.5.4 Data Transfer Protocols
        1. 6.5.4.1 Protocols for Configuring the Device
        2. 6.5.4.2 Protocols for Reading From the Device
          1. 6.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 6.5.4.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 6.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 6.5.4.2.3.1 Output Clock Source Options with SRC Protocols
            2. 6.5.4.2.3.2 Bus Width Options With SRC Protocols
            3. 6.5.4.2.3.3 Output Data Rate Options With SRC Protocols
      5. 6.5.5 Device Setup
        1. 6.5.5.1 Single Device: All multiSPI Options
        2. 6.5.5.2 Single Device: Minimum Pins for a Standard SPI
        3. 6.5.5.3 Multiple Devices: Daisy-Chain Topology
        4. 6.5.5.4 Multiple Devices: Star Topology
  8. 7 Register Maps
    1. 7.1 Device Configuration and Register Maps
      1. 7.1.1 PD_CNTL Register (address = 04h) [reset = 08h]
      2. 7.1.2 SDI_CNTL Register (address = 008h) [reset = 00h]
      3. 7.1.3 SDO_CNTL Register (address = 0Ch) [reset = 00h]
      4. 7.1.4 DATA_CNTL Register (address = 010h) [reset = 00h]
      5. 7.1.5 PATN_LSB Register (address = 014h) [reset = 00h]
      6. 7.1.6 PATN_MID Register (address = 015h) [reset = 00h]
      7. 7.1.7 PATN_MSB Register (address = 016h) [reset = 00h]
      8. 7.1.8 OFST_CAL Register (address = 020h) [reset = 00h]
      9. 7.1.9 REF_MRG Register (address = 030h) [reset = 00h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. 8.1.2.1 Charge-Kickback Filter
        2. 8.1.2.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
    3. 8.3 Power-Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Signal Path
        2. 8.4.1.2 Grounding and PCB Stack-Up
        3. 8.4.1.3 Decoupling of Power Supplies
        4. 8.4.1.4 Reference Decoupling
        5. 8.4.1.5 Differential Input Decoupling
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5.3 Interleaving Conversion Cycles and Data Transfer Frames

The host controller operates the device at the desired throughput by interleaving the conversion cycles and the data transfer frames.

The cycle time of the device, tcycle, is the time difference between two consecutive CONVST rising edges provided by the host controller. The response time of the device, tresp, is the time difference between the host controller initiating conversion C, and the host controller receiving the complete result for conversion C.

Figure 6-15 shows three conversion cycles: C, C + 1, and C + 2. Conversion C is initiated by a CONVST rising edge at time t = 0, and the conversion result becomes available for data transfer at tconv. However, this result is loaded into the ODR only on the subsequent CS falling edge. This CS falling edge must be provided before the completion of conversion C + 1 (that is, before tcycle + tconv).

To achieve the rated performance specifications, the host controller must make sure that no digital signals toggle during the quiet acquisition time (tqt_acq) and quiet aperture time (td_cnvcap). Any noise during td_cnvcap can negatively affect the result of the ongoing conversion, whereas any noise during tqt_acq can negatively affect the result of the subsequent conversion.

ADS8920B ADS8922B ADS8924B Data Transfer ZonesFigure 6-15 Data Transfer Zones

This architecture allows for two distinct time zones (zone 1 and zone 2) to transfer data for each conversion. Zone 1 and zone 2 for conversion C are defined in Table 6-3.

Table 6-3 Data Transfer Zones Timing
ZONESTARTING TIMEENDING TIME
Zone 1 for conversion C t conv t cycle − t qt\_aq
Zone 2 for conversion C t cycle + t d\_cn vcap t cycle + t cycle − t qt\_acq

The response time includes the conversion time and the data transfer time, and thus is a function of the selected data transfer zone.

Figure 6-16 and Figure 6-17 illustrate interleaving of three conversion cycles (C, C + 1, and C + 2) with three data transfer frames (F, F + 1, and F + 2) in zone 1 and in zone 2, respectively.

ADS8920B ADS8922B ADS8924B Zone 1 Data TransferFigure 6-16 Zone 1 Data Transfer
ADS8920B ADS8922B ADS8924B Zone 2 Data TransferFigure 6-17 Zone 2 Data Transfer

To achieve cycle time tcycle, the read time in zone 1 is given by Equation 6:

Equation 6. t read-Z1 ≤ t cycle − t conv − t qt\_acq

For an optimal data transfer frame, Equation 6 results in an SCLK frequency given by Equation 7:

Equation 7. f SCLK ≥ 16 t read-Z1

Then, the zone 1 data transfer achieves a response time defined by Equation 8:

Equation 8. t resp-Z1-min = t conv + t read-Z1

At lower SCLK speeds, tread-Z1 increases, resulting in slower response times and higher cycle times.

To achieve the same cycle time, tcycle, the read time in zone 2 is given by Equation 9:

Equation 9. t read-Z2 ≤ t cycle − t d\_cnvcap − t qt\_acq

For an optimal data transfer frame, Equation 9 results in an SCLK frequency given by Equation 10:

Equation 10. f SCLK ≥ 16 t read-Z2

Then, the zone 2 data transfer achieves a response time defined by Equation 11:

Equation 11. t resp-Z2-min = t cycle + t d\_cn vcap + t read-Z2

Any increase in tread-Z2 increases response time and can increase cycle time.

For a given cycle time, the zone 1 data transfer clearly achieves faster response time, but also requires a higher SCLK speed (as evident from Equation 6, Equation 7, and Equation 8); whereas, the zone 2 data transfer clearly requires a lower SCLK speed but has a slower response time (as evident from Equation 9, Equation 10, and Equation 11).

Note:

A data transfer frame can begin in zone 1, and then extend into zone 2; however, the host controller must make sure that no digital transitions occur during the tqt_acq and td_cnvcap time intervals.

Note:

For data transfer operations in zone 2 using the ADC-Clock-Master protocol
(SDO_MODE[1:0] = 11b), the device supports only the external-clock-echo option
(SSYNC_CLK_SEL[1:0] = 00b); see Table 6-9.