SBAS689D June   2015  – December 2016 AFE4404

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TIA and Switched RC Filter
        1. 8.3.1.1 Operation with Two and Three LEDs
          1. 8.3.1.1.1 LED Current Setting
        2. 8.3.1.2 TIA Gain Settings
        3. 8.3.1.3 TIA Bandwidth Settings
      2. 8.3.2 Power Management
        1. 8.3.2.1 Transmitter Supply (TX_SUP)
        2. 8.3.2.2 Receiver Supply (RX_SUP)
        3. 8.3.2.3 I/O Supply (IO_SUP)
        4. 8.3.2.4 Boost Converters Selection
      3. 8.3.3 Offset Cancellation DAC
        1. 8.3.3.1 Offset Cancellation DAC Controls
      4. 8.3.4 Analog-to-Digital Converter (ADC)
      5. 8.3.5 I2C Interface
      6. 8.3.6 Timing Engine
        1. 8.3.6.1 Timer and PRF Controls
        2. 8.3.6.2 Timing Control Registers
        3. 8.3.6.3 Receiver Timing
        4. 8.3.6.4 Dynamic Power-Down Timing
        5. 8.3.6.5 Sample Register Values
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
      2. 8.4.2 RESET Modes
      3. 8.4.3 Clocking Modes
      4. 8.4.4 PRF Programmability
      5. 8.4.5 Averaging Modes
      6. 8.4.6 Decimation Mode
        1. 8.4.6.1 Decimation Mode Power and Performance
    5. 8.5 Register Map
      1. 8.5.1  Register 0h (address = 0h) [reset = 0h]
      2. 8.5.2  Register 1h (address = 1h) [reset = 0h]
      3. 8.5.3  Register 2h (address = 2h) [reset = 0h]
      4. 8.5.4  Register 3h (address = 3h) [reset = 0h]
      5. 8.5.5  Register 4h (address = 4h) [reset = 0h]
      6. 8.5.6  Register 5h (address = 5h) [reset = 0h]
      7. 8.5.7  Register 6h (address = 6h) [reset = 0h]
      8. 8.5.8  Register 7h (address = 7h) [reset = 0h]
      9. 8.5.9  Register 8h (address = 8h) [reset = 0h]
      10. 8.5.10 Register 9h (address = 9h) [reset = 0h]
      11. 8.5.11 Register Ah (address = Ah) [reset = 0h]
      12. 8.5.12 Register Bh (address = Bh) [reset = 0h]
      13. 8.5.13 Register Ch (address = Ch) [reset = 0h]
      14. 8.5.14 Register Dh (address = Dh) [reset = 0h]
      15. 8.5.15 Register Eh (address = Eh) [reset = 0h]
      16. 8.5.16 Register Fh (address = Fh) [reset = 0h]
      17. 8.5.17 Register 10h (address = 10h) [reset = 0h]
      18. 8.5.18 Register 11h (address = 11h) [reset = 0h]
      19. 8.5.19 Register 12h (address = 12h) [reset = 0h]
      20. 8.5.20 Register 13h (address = 13h) [reset = 0h]
      21. 8.5.21 Register 14h (address = 14h) [reset = 0h]
      22. 8.5.22 Register 15h (address = 15h) [reset = 0h]
      23. 8.5.23 Register 16h (address = 16h) [reset = 0h]
      24. 8.5.24 Register 17h (address = 17h) [reset = 0h]
      25. 8.5.25 Register 18h (address = 18h) [reset = 0h]
      26. 8.5.26 Register 19h (address = 19h) [reset = 0h]
      27. 8.5.27 Register 1Ah (address = 1Ah) [reset = 0h]
      28. 8.5.28 Register 1Bh (address = 1Bh) [reset = 0h]
      29. 8.5.29 Register 1Ch (address = 1Ch) [reset = 0h]
      30. 8.5.30 Register 1Dh (address = 1Dh) [reset = 0h]
      31. 8.5.31 Register 1Eh (address = 1Eh) [reset = 0h]
      32. 8.5.32 Register 20h (address = 20h) [reset = 0h]
      33. 8.5.33 Register 21h (address = 21h) [reset = 0h]
      34. 8.5.34 Register 22h (address = 22h) [reset = 0h]
      35. 8.5.35 Register 23h (address = 23h) [reset = 0h]
      36. 8.5.36 Register 29h (address = 29h) [reset = 0h]
      37. 8.5.37 Register 2Ah (address = 2Ah) [reset = 0h]
      38. 8.5.38 Register 2Bh (address = 2Bh) [reset = 0h]
      39. 8.5.39 Register 2Ch (address = 2Ch) [reset = 0h]
      40. 8.5.40 Register 2Dh (address = 2Dh) [reset = 0h]
      41. 8.5.41 Register 2Eh (address = 2Eh) [reset = 0h]
      42. 8.5.42 Register 2Fh (address = 2Fh) [reset = 0h]
      43. 8.5.43 Register 31h (address = 31h) [reset = 0h]
      44. 8.5.44 Register 32h (address = 32h) [reset = 0h]
      45. 8.5.45 Register 33h (address = 33h) [reset = 0h]
      46. 8.5.46 Register 34h (address = 34h) [reset = 0h]
      47. 8.5.47 Register 35h (address = 35h) [reset = 0h]
      48. 8.5.48 Register 36h (address = 36h) [reset = 0h]
      49. 8.5.49 Register 37h (address = 37h) [reset = 0h]
      50. 8.5.50 Register 39h (address = 39h) [reset = 0h]
      51. 8.5.51 Register 3Ah (address = 3Ah) [reset = 0h]
      52. 8.5.52 Register 3Dh (address = 3Dh) [reset = 0h]
      53. 8.5.53 Register 3Fh (address = 3Fh) [reset = 0h]
      54. 8.5.54 Register 40h (address = 40h) [reset = 0h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 System-Level ESD Considerations
        2. 9.2.2.2 Reducing Sensitivity to Ambient Light Modulation
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Choosing the Right AFE Settings
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YZP|15
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range RX_SUP to GND –0.3 4 V
IO_SUP to GND –0.3 4
RX_SUP-IO_SUP –0.3
TX_SUP to GND –0.3 6
Voltage applied to analog inputs Max [–0.3, (GND – 0.3)] Min [4, (RX_SUP + 0.3)] V
Voltage applied to digital inputs Max [–0.3, (GND – 0.3)] Min [4, (IO_SUP + 0.3)] V
Maximum duty cycle (cumulative):
sum of all LED phase durations as a function
of the total period
50-mA LED current mode
(ILED_2X = 0)
10%
100-mA LED current mode
(ILED_2X = 1)
3%
Storage temperature, Tstg –60 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
RX_SUP Receiver supply 2 3.6 V
IO_SUP Input/output supply 1.7 Min (3.6, RX_SUP) V
TX_SUP Transmitter supply 50-mA LED current mode
(ILED_2X = 0)
3.0 or (0.5 + VLED)(1),
whichever is greater
5.25 V
100-mA LED current mode
(ILED_2X = 1)
3.0 or (1.0 + VLED)(1),
whichever is greater
5.25
Digital inputs 0 IO_SUP V
Analog inputs 0 RX_SUP V
Operating temperature range –20 70 °C
VLED refers to the maximum voltage drop across the external LED (at maximum LED current). This value is usually governed by the forward drop voltage (VFB) of the LED.

Thermal Information

THERMAL METRIC(1) AFE4404 UNIT
YZP (DSBGA)
15 BALLS
RθJA Junction-to-ambient thermal resistance 67.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 0.5 °C/W
RθJB Junction-to-board thermal resistance 12.9 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 12.9 °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics

Minimum and maximum specifications are at TA = –20°C to 70°C, typical specifications are at 25°C. TX_SUP = 4 V, RX_SUP = IO_SUP = 3 V, 100-Hz PRF, 8-MHz external clock (with CLKDIV_EXTMODE set to divide-by-2), detector CIN = 50 pF, and CLKDIV_PRF set to 1, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PULSE REPETITION FREQUENCY
PRF(1) Pulse repetition frequency 10(7) 1000 SPS
RECEIVER
Offset cancellation DAC current range –7 to 7 µA
Offset cancellation DAC current step 0.47 µA
TIA gain setting 10k to 2M Ω
Cf setting 2.5 to 25 pF
Switched RC filter bandwidth 2.5(2) kHz
ADC averages 1 16
Detector capacitance Differential capacitance between INP, INN 10 200 pF
TRANSMITTER
LED current range ILED_2X = 0 0 to 50 mA
ILED_2X = 1 0 to 100
LED current resolution 6 Bits
CLOCKING (Internal Oscillator)
Frequency 4 MHz
Accuracy Room temperature ±1%
Frequency drift with temperature Full temperature range ±0.5%
Jitter (RMS) 100 ps
Output clock high level IO_SUP V
Output clock low level 0 V
Output clock rise and fall times 10% to 90%, 15-pF load capacitance on
CLK pin
< 30 ns
CLOCKING (External Clock)
Frequency range(3) 4 60 MHz
Input clock high level IO_SUP V
Input clock low level 0 V
Input capacitance of CLK pin Capacitance to ground < 4 pF
I2C INTERFACE
Maximum clock speed 400 kHz
I2C slave address 58 Hex
PERFORMANCE
Receiver SNR SNR over a 20-Hz bandwidth for a 500-kΩ gain setting, 50% FS output, 2% LED and sampling pulse duration,
ADC averages set to 16
100 dBFS(6)
Transmitter SNR SNR over a 20-Hz bandwidth for a 50-mA LED current setting 100 dBFS(6)
CURRENT CONSUMPTION
RX_SUP current Normal operation, in dynamic power-down mode(8) 300 µA
Always ON receiver, external clock mode 620
Always ON receiver, internal oscillator mode 670
Hardware power-down (PWDN) mode(9) 3
Software power-down (PDNAFE) mode(9) 35
IO_SUP current Normal operation, in dynamic power-down mode(8) 20 µA
Always ON receiver, external clock mode 20
Always ON receiver, internal oscillator mode 5
Hardware power-down (PWDN) mode(9) 3
Software power-down (PDNAFE) mode(9) 5
TX_SUP current Normal operation, in dynamic power-down mode(8)(10) 5 µA
Always ON receiver, external clock mode(10) 25
Always ON receiver, internal oscillator mode(10) 25
Hardware power-down (PWDN) mode(9)(10) 2
Software power-down (PDNAFE) mode(9)(10) 2
TRANSIENT RECOVERY
tACTIVE Recovery from PWDN mode Time for signal chain to be functional(4) 10 ms
tCHANNEL Recovery from any event causing a change in signal characteristics PRF = 100 Hz, sampling duty cycle
(each phase) of 2%(5)
200 ms
DIGITAL INPUTS
VIH High-level input voltage 0.9 × IO_SUP IO_SUP V
VIL Low-level input voltage 0 0.1 × IO_SUP V
DIGITAL OUTPUTS
VOH High-level output voltage IO_SUP V
VOL Low-level output voltage 0 V
PRF refers to the rate at which samples from each of the four phases are output from the AFE.
The effective bandwidth of the switched RC filter scales as a function of the sampling duty cycle. For example, at 2% sampling width duty cycle, the effective bandwidth of the switched RC filter is approximately 50 Hz.
With appropriate setting of the clock divider ratio (CLKDIV_EXTMODE).
For full performance to be restored, a longer time as governed by tCHANNEL can be applicable.
tCHANNELscales inversely with the sampling duty cycle.
dBFS refers to a full-scale voltage of 2 V.
To extend the lower range of PRF down to 10 Hz, program the CLKDIV_PRF setting.
In dynamic power-down mode for 90% and active mode for 10% of the period.
External clock mode with the external clock switched off.
LED currents set to 0 mA.

Timing Requirements

MIN TYP MAX UNIT
tI2C_RISE I2C data rise time with a 10-kΩ pullup resistor with a 20-pF load from I2C data to GND 1200 ns
tI2C_FALL I2C data fall time (when the data line is pulled down by the AFE) with a 20-pF load from I2C data to GND 28 ns
tADC_RDY_RISE ADC_RDY rise time (10% to 90%) with a 15-pF capacitive load to ground 21 ns
tADC_RDY_FALL ADC_RDY fall time (90% to 10%) with a 15-pF capacitive load to ground 21 ns

Typical Characteristics

At 25°C, TX_SUP = 4 V, RX_SUP = IO_SUP = 3.3 V, 100-Hz PRF, 25% duty cycle, Rf = 500 kΩ, Cf is adjusted to keep the TIA time constant at 1/10th of the sampling duration, 8-MHz external clock (with CLKDIV_EXTMODE set to divide-by-2), CLKDIV_PRF = 1, detector CIN = 50 pF, ADC averaging = max allowed, SNR (dBFS) = noise referred to full-scale range of 2 V, noise integrated from 1 Hz to Nyquist (= PRF / 2), and values assigned to CLKDIV_EXTMODE and CLK_DIV_PRF parameters correspond to division ratios controlled by these modes, unless otherwise specified.
AFE4404 D001_BAS689.gif
Figure 1. Receiver Current vs External Clock Frequency
AFE4404 D003_BAS689.gif
Duty cycle (x-axis) refers to the sampling duration expressed as a percentage of the pulse repetition period.
Figure 3. Input-Referred Noise Current in 20-Hz Bandwidth vs Duty Cycle for Different Output Levels
(As a Percentage of Full-Scale)
AFE4404 D005_BAS689.gif
Figure 5. Receiver Input-Referred Noise Current in 20-Hz BW vs Duty Cycle (Different TIA Gain Settings)
AFE4404 D006_BAS689.gif
Figure 7. Receiver Input-Referred Noise Current over Nyquist Bandwidth vs Duty Cycle (Different ADC Averaging)
AFE4404 D022_BAS689.gif
Figure 9. Input-Referred Noise Current in Nyquist Bandwidth vs Duty Cycle (Different Decimation Factor)
AFE4404 D009_BAS689.gif
PRF = 2000 Hz
Figure 11. Response of the Switched-RC Filter
at the AFE Output
AFE4404 D019_BAS689.gif
Figure 13. Filter Response for Multiple PRFs at
5% Duty Cycle
AFE4404 D015_BAS689.gif
Figure 15. LED Current vs Transmitter Headroom Voltage
AFE4404 D014_BAS689.gif
Figure 17. Transmitter DAC Current Step Error in
100-mA Mode
AFE4404 D017_BAS689.gif
Duty cycle = 1%
Figure 19. PSRR vs Tone Frequency at RX_SUP
AFE4404 D020_BAS689.gif
Figure 21. Receiver SNR in a 20-Hz Bandwidth vs
Duty Cycle Across Different Temperatures
AFE4404 D002_BAS689.gif
Active window = 500 µs, LED pulse = 100 µs,
all four DYNAMIC bits set to 1
Figure 2. Receiver Current vs PRF in
Dynamic Power-Down Mode
AFE4404 D004_BAS689.gif
Duty cycle (x-axis) refers to the sampling duration expressed as a percentage of the pulse repetition period.
Figure 4. Signal-to-Noise Ratio in 20-Hz Bandwidth vs Duty Cycle for Different Output Levels
(As a Percentage of Full-Scale)
AFE4404 D008_BAS689.gif
Figure 6. Receiver SNR in 20-Hz BW vs Duty Cycle
(Different TIA Gain Settings)
AFE4404 D007_BAS689.gif
Figure 8. Receiver Signal-to-Noise Ratio over Nyquist Bandwidth vs Duty Cycle (Different ADC Averaging)
AFE4404 D010_BAS689.gif
Figure 10. Receiver Input-Referred Noise in 20-Hz Bandwidth vs Duty Cycle
(Different Offset Cancellation DAC Currents)
AFE4404 D016_BAS689.gif
Figure 12. Filter Response for Multiple PRFs at
1% Duty Cycle
AFE4404 D012_BAS689.gif
Figure 14. Transmitter Current Linearity
AFE4404 D013_BAS689.gif
Figure 16. Transmitter DAC Current Step Error in
50-mA Mode
AFE4404 D018_BAS689.gif
Duty cycle = 1%
Figure 18. PSRR vs Tone Frequency at TX_SUP
AFE4404 D011_BAS689.gif
PRF = 200 Hz, NUMAV = 0
Figure 20. Rejection of a 50-Hz Differential Tone Across Spacing Between LED and Ambient Phases
AFE4404 D021_BAS689.gif
Figure 22. Internal Oscillator Frequency vs
Temperature on a Typical Unit