SBAS689D June   2015  – December 2016 AFE4404


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 TIA and Switched RC Filter
        1. Operation with Two and Three LEDs
          1. LED Current Setting
        2. TIA Gain Settings
        3. TIA Bandwidth Settings
      2. 8.3.2 Power Management
        1. Transmitter Supply (TX_SUP)
        2. Receiver Supply (RX_SUP)
        3. I/O Supply (IO_SUP)
        4. Boost Converters Selection
      3. 8.3.3 Offset Cancellation DAC
        1. Offset Cancellation DAC Controls
      4. 8.3.4 Analog-to-Digital Converter (ADC)
      5. 8.3.5 I2C Interface
      6. 8.3.6 Timing Engine
        1. Timer and PRF Controls
        2. Timing Control Registers
        3. Receiver Timing
        4. Dynamic Power-Down Timing
        5. Sample Register Values
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
      2. 8.4.2 RESET Modes
      3. 8.4.3 Clocking Modes
      4. 8.4.4 PRF Programmability
      5. 8.4.5 Averaging Modes
      6. 8.4.6 Decimation Mode
        1. Decimation Mode Power and Performance
    5. 8.5 Register Map
      1. 8.5.1  Register 0h (address = 0h) [reset = 0h]
      2. 8.5.2  Register 1h (address = 1h) [reset = 0h]
      3. 8.5.3  Register 2h (address = 2h) [reset = 0h]
      4. 8.5.4  Register 3h (address = 3h) [reset = 0h]
      5. 8.5.5  Register 4h (address = 4h) [reset = 0h]
      6. 8.5.6  Register 5h (address = 5h) [reset = 0h]
      7. 8.5.7  Register 6h (address = 6h) [reset = 0h]
      8. 8.5.8  Register 7h (address = 7h) [reset = 0h]
      9. 8.5.9  Register 8h (address = 8h) [reset = 0h]
      10. 8.5.10 Register 9h (address = 9h) [reset = 0h]
      11. 8.5.11 Register Ah (address = Ah) [reset = 0h]
      12. 8.5.12 Register Bh (address = Bh) [reset = 0h]
      13. 8.5.13 Register Ch (address = Ch) [reset = 0h]
      14. 8.5.14 Register Dh (address = Dh) [reset = 0h]
      15. 8.5.15 Register Eh (address = Eh) [reset = 0h]
      16. 8.5.16 Register Fh (address = Fh) [reset = 0h]
      17. 8.5.17 Register 10h (address = 10h) [reset = 0h]
      18. 8.5.18 Register 11h (address = 11h) [reset = 0h]
      19. 8.5.19 Register 12h (address = 12h) [reset = 0h]
      20. 8.5.20 Register 13h (address = 13h) [reset = 0h]
      21. 8.5.21 Register 14h (address = 14h) [reset = 0h]
      22. 8.5.22 Register 15h (address = 15h) [reset = 0h]
      23. 8.5.23 Register 16h (address = 16h) [reset = 0h]
      24. 8.5.24 Register 17h (address = 17h) [reset = 0h]
      25. 8.5.25 Register 18h (address = 18h) [reset = 0h]
      26. 8.5.26 Register 19h (address = 19h) [reset = 0h]
      27. 8.5.27 Register 1Ah (address = 1Ah) [reset = 0h]
      28. 8.5.28 Register 1Bh (address = 1Bh) [reset = 0h]
      29. 8.5.29 Register 1Ch (address = 1Ch) [reset = 0h]
      30. 8.5.30 Register 1Dh (address = 1Dh) [reset = 0h]
      31. 8.5.31 Register 1Eh (address = 1Eh) [reset = 0h]
      32. 8.5.32 Register 20h (address = 20h) [reset = 0h]
      33. 8.5.33 Register 21h (address = 21h) [reset = 0h]
      34. 8.5.34 Register 22h (address = 22h) [reset = 0h]
      35. 8.5.35 Register 23h (address = 23h) [reset = 0h]
      36. 8.5.36 Register 29h (address = 29h) [reset = 0h]
      37. 8.5.37 Register 2Ah (address = 2Ah) [reset = 0h]
      38. 8.5.38 Register 2Bh (address = 2Bh) [reset = 0h]
      39. 8.5.39 Register 2Ch (address = 2Ch) [reset = 0h]
      40. 8.5.40 Register 2Dh (address = 2Dh) [reset = 0h]
      41. 8.5.41 Register 2Eh (address = 2Eh) [reset = 0h]
      42. 8.5.42 Register 2Fh (address = 2Fh) [reset = 0h]
      43. 8.5.43 Register 31h (address = 31h) [reset = 0h]
      44. 8.5.44 Register 32h (address = 32h) [reset = 0h]
      45. 8.5.45 Register 33h (address = 33h) [reset = 0h]
      46. 8.5.46 Register 34h (address = 34h) [reset = 0h]
      47. 8.5.47 Register 35h (address = 35h) [reset = 0h]
      48. 8.5.48 Register 36h (address = 36h) [reset = 0h]
      49. 8.5.49 Register 37h (address = 37h) [reset = 0h]
      50. 8.5.50 Register 39h (address = 39h) [reset = 0h]
      51. 8.5.51 Register 3Ah (address = 3Ah) [reset = 0h]
      52. 8.5.52 Register 3Dh (address = 3Dh) [reset = 0h]
      53. 8.5.53 Register 3Fh (address = 3Fh) [reset = 0h]
      54. 8.5.54 Register 40h (address = 40h) [reset = 0h]
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. System-Level ESD Considerations
        2. Reducing Sensitivity to Ambient Light Modulation
      3. 9.2.3 Application Curves
        1. Choosing the Right AFE Settings
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • YZP|15
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The AFE is designed to operate with a minimal number of external components. Deriving the power supplies for the AFE from the available source of power in the system can require an additional external LDO or boost converter. A reset is essential after power-up to ensure that all registers are reset to their default values. TI also recommends that the entire system be operated using a single master clock. The AFE can either be set to accept an external clock derived from a master clock generated elsewhere in the system, or the AFE can provide its internal oscillator as an output clock to serve as the master clock for the rest of the system. If a single master clock is not possible, extra care must be taken to ensure that spurious energy from unrelated clocks does not get coupled into the AFE. If this energy does couple into the AFE the spurs get aliased based on the sampling operation. These aliased spurs can result in a faulty detection of parameters (such as heart rate). The photodiode outputs are specifically prone to picking up noise. Especially when operating in coexistence and close proximity with RF communication circuitry [such as Bluetooth® low energy (BLE)], a common-mode choke may become essential to add in the path of the AFE inputs to reject the interference.

Typical Application

AFE4404 App_Dgrm_BAS689.gif
NOTE: Use Rseries in external clock mode and Rshunt in internal oscillator mode.
Figure 92. Typical AFE Connection

Figure 92 illustrates the typical connection of the AFE. The following points are to be noted:

  1. Use decoupling capacitors (1 µF or higher) placed close to the device to filter noise on RX_SUP and TX_SUP.
  2. The voltage level used for IO_SUP must be the same as the I/O voltage level for the MCU.
  3. In external clock mode, TI recommends connecting a series resistor (Rseries) on the CLK pin. At power-up and before a RESET pulse is applied, the register bits can be in an uninitialized state. The CLK pin can possibly be configured as an output pin in this uninitialized state because the CLK pin is an I/O pin. In such a scenario, Rseries limits the current (because the MCU also attempts to drive the CLK pin). For maximum frequency of the external clock (60 MHz), the Rseries value is recommended to be 500 Ω.
  4. In internal oscillator mode, a shunt resistor (Rshunt) equal to 500 kΩ is recommended to be connected to the CLK pin. At power-up and after reset, the device resets to the default mode of the external clock. The CLK pin is in a tri-state mode until the internal clock mode with the CLK output enabled is written through the I2C interface. The function of Rshunt is to pull down the CLK pin to a logic level of 0 so that the input clock to the MCU is at a logic level even when the CLK pin is tri-stated.
  5. When in power-down mode (PWDN and PDNAFE) the CLK pin must be shut off (tri-stated or driven to zero), if externally driven.

Design Requirements

The AFE architecture is very flexible, and can be used for both high-performance saturation of peripheral capillary oxygen (SpO2) applications as well as low-power, battery-operated heart-rate monitoring (HRM) applications as a result of this flexibility. The high dynamic range of the AFE enables excellent SNR for the signal of interest (usually small in amplitude) even in the presence of large-signal artifacts resulting from ambient and motion changes.

Detailed Design Procedure

The following important factors are key to extracting the full performance benefit from the AFE:

  1. Good optics including bright LEDs and high-sensitivity photodiodes
  2. Good mechanical design
  3. A calibration loop that sets the optimal AFE settings based on the signal conditions

TI recommends that a system-level budgeting of dynamic range be initially done based on the following factors:

  1. The range of the dc signal currents that are input to the AFE
  2. The range of ac-to-dc ratio across different users
  3. Signal current changes expected from artifacts (such as motion and ambient light changes)
  4. The SNR required for heart-rate extraction algorithms to function successfully

Based on the above analysis, the available dynamic range from the AFE (approximately 100 dB) can be partitioned between the various components, and the target dc level for the calibration algorithm can also be arrived at.

System-Level ESD Considerations

To meet system-level ESD requirements, additional on-board ESD protection diodes may be required to be connected to the AFE4404 input pins. The input pins are sensitive to leakage, so using low-leakage ESD diodes is recommended for protecting these pins.

TI’s portfolio of ESD protection devices can be accessed at the Overview for ESD Protection Diodes page.

The ESD Protection Layout Guide (SLVA680) is available for download at

Reducing Sensitivity to Ambient Light Modulation

Ambient light has an additive effect to the LED phase output of the AFE because ambient light occurs on the photodiode in a manner similar to the light originating from the LED. Any artifacts in ambient light can therefore interfere with the extraction of the heart rate from the signal in the LED phase. The purpose of subtracting the ambient phase signal from the LED phase signal is to remove this effect. If the effect of ambient light on the LED and ambient phase outputs is unequal, then subtraction of the ambient phase data from the LED phase data gives only an incomplete cancellation of the ambient light modulation effect. In that case, a periodic pattern in the ambient light can cause spurious tones to appear in the (LED-Ambient) data. The following guidelines can significantly reduce the sensitivity of the AFE to ambient light modulation:

  • Follow the timing guidelines listed in Table 7.
  • t1 (the start of the LED to the start of sampling) plays a role in the sensitivity to ambient light modulation. For best performance under high ambient light modulation, keeping t1 to a value greater than 25 µs is recommended even when operating at low sampling pulse durations.
  • The TIA maintains the photodiode bias through negative feedback. If the TIA output saturates, then the photodiode bias is disturbed. The associated transient for the photodiode bias to get restored can increase the sensitivity to ambient light modulation. For example, a saturation of the TIA output during the LED3 phase can lead to the TIA recovery response to span both the LED1 and Ambient1 phases. This scenario can cause the channel response to differ between these two phases, thereby rendering the ambient subtraction through (LED1-Ambient1) to be incomplete. Therefore, the output of every phase is recommended to be prevented from saturating (through periodic signal monitoring and gain adjustment) even if the data from that phase is not being used by the heart rate estimation algorithm.
  • If the ambient light changes at a fast rate, the effective ambient signal observed during the LED and ambient phases can be different because of the difference between the sampling instants. This effect can also cause the ambient subtraction to be incomplete. Reducing the spacing between the sampling instants of the LED and ambient can reduce this effect.

Figure 93 is the AFE output in the ambient phase resulting from modulation applied to the ambient light. Figure 94 is the (LED-Ambient) phase data with non-optimal settings and Figure 95 is the (LED-Ambient) phase data with optimal settings.

AFE4404 D030_BAS689.gif
Figure 93. Ambient Data with Ambient Light Modulation
AFE4404 D032_BAS689.gif
Figure 95. (LED-Ambient) Data with an Optimal AFE Setting
AFE4404 D031_BAS689.gif
Figure 94. (LED-Ambient) Data with a Non-Optimal AFE Setting

Application Curves

This section outlines the trends described in the Typical Characteristics section from an application perspective.

Figure 1 illustrates the receiver current across different external clock frequencies. Each of the curves corresponds to a different CLKDIV_EXTMODE setting that determines the division ratio between the external clock and the internal clock (CLK_INT). The internal clock frequency must be in the range of 4 MHz to 6 MHz for proper operation, and each curve corresponds to a sweep of the external clock frequency that corresponds to an internal clock frequency sweep over the range of 4 MHz to 6 MHz.

Figure 2 illustrates the receiver current across the PRF with the dynamic power-down signal (PDN_CYCLE) enabled during the portion of the period when the receiver does not need to be active. The active period is maintained as 500 µs for each PRF setting and the device is in power-down mode (set by PDN_CYCLE) for the rest of the period. Additionally, the timing margins indicated as t8 and t9 in Figure 35 are included before and after the PDN_CYCLE pulse. The fraction of time that the device is in power-down mode over a period increases with reduction in the PRF because the period scales inversely with PRF. This timing is the reason why the curve displays a reduction in the average receiver current with reduction in PRF. The curve corresponding to CLKDIV_PRF = 1 terminates at a lower PRF of approximately 61 Hz, which is determined by the maximum range of the 16-bit timing counter (4 MHz divided by 216). With the CLKDIV_PRF set to 16, the timer clock is divided by 16. Thus, the lower PRF range can be extended down to a few hertz (the recommended operation is to restrict the range to 10 Hz or higher). For the same PRF (for example 100 Hz), a higher CLKDIV_PRF setting results in a lower power consumption because the timer engine runs on a slower clock and takes less switching current.

The noise plots from Figure 3 to Figure 7 are taken at a PRF of 100 Hz. For this PRF setting, the noise at the output of the AFE is distributed from 0 Hz to 50 Hz. Plots that indicate the noise as over Nyquist bandwidth have integrated noise from 1 Hz to 50 Hz. The plots that indicate the noise as over 20-Hz bandwidth have integrated noise until 20 Hz. These plots are suitable for when additional low-pass filtering is implemented in the MCU to limit the noise bandwidth (in this case, to 20 Hz). This low-pass filtering can improve SNR because the PPG signal has information contained in the frequency band below 10 Hz.

Figure 3 illustrates the input-referred noise current versus sampling duration duty cycle for different voltage levels at the receiver output. The PPG signal has a dc component that can cause the signal at the output of the receiver to be anywhere between ±FS (full-scale). The curves in Figure 3 illustrate a slight increase in the noise around higher dc levels, which results from additional noise sources in the ADC. The input-referred noise current can be visualized as a noise current flowing into one of the input pins (for instance, INP) and flowing out of the other (for example, INM). The noise is computed on the samples that constitute the difference between the LED phase and the ambient phase.

Figure 4 illustrates the SNR plots corresponding to the same data as Figure 3. The input-referred noise and SNR can be related as follows: the input-referred noise current can be first referred to the receiver output using a factor of 2Rf, where Rf is 500 kΩ for this case. This output-referred voltage gives the output noise that can then be referred to the full-scale value of 2 V (note that when the full-scale differential input to the ADC is 2.4 VPP, the operating range is 2 VPP, which is the valid operating range of the TIA).

Figure 5 plots the input-referred noise current versus sampling duty cycle across different TIA gain settings.

Figure 6 corresponds to the SNR plot of the data in Figure 5. As illustrated in Figure 5, a dynamic range of 100 dB or more can be achieved in the receiver for many of the TIA gain settings. A reduction in SNR for higher TIA gain settings is in line with what is expected from the receiver because a higher TIA gain setting implies a lower signal level at the input of the receiver.

Figure 7 and Figure 8 correspond to the input-referred noise current and corresponding SNR across the sampling duration duty cycle for different settings of the ADC averaging (as set by the NUMAV register setting). An ADC averaging of 1 implies no averaging. As illustrated in these curves, the SNR improves with averaging more samples. This improvement becomes more pronounced at lower TIA gain settings where the ADC noise has a higher affect on the overall receiver noise.

The input-referred current noise current versus sampling duty cycle for different decimation factors is illustrated in Figure 9. As illustrated in Figure 9, a 4X decimation leads to almost a 2X reduction in input-referred noise.

Figure 10 refers to a hypothetical case that is used to illustrate the improvement in the receiver dynamic range when using the offset cancellation DAC. Assume that the dc level of the signal current corresponds to 7.25 µA. Without the offset cancellation DAC, assume operation is with a TIA gain of 25 kΩ, which causes the output of the receiver to be at 362.5 mV. If the offset cancellation DAC is enabled with a subtraction current of 7 µA (the maximum setting), then the signal level at the input of the TIA after the offset cancellation DAC subtraction is 0.25 µA. For this current, a TIA gain setting of 1 MΩ causes the TIA output to be at 500 mV. In effect, by enabling the offset cancellation DAC with the right setting, a higher TIA gain setting is allowed, which ends up reducing the contribution of the ADC noise and thereby reduces the input-referred noise current of the receiver. Note that the benefit from the offset cancellation DAC may not be so dramatic in an actual use case because perfect cancellation of the dc signal may not be achieved from the 0.5-µA resolution of the offset cancellation DAC. Even if achieved, the highest possible TIA gain setting on the residual current may cause receiver saturation with small changes in the dc signal level. For this reason, a safe value for the maximum gain setting when operating with the offset cancellation DAC is 250 kΩ or less. The third curve in Figure 10 illustrates this case.

Figure 11 illustrates the effective response of the switched RC filter at the receiver output. The switched RC filter has a physical RC time constant that corresponds to a bandwidth of approximately 2.5 kHz. However, the effective bandwidth of the filter scales approximately with the sampling duration duty cycle. For a lower duty cycle, the effective filter bandwidth reduces as described from the comparison of a 5% duty cycle with a 25% duty cycle. At even lower duty cycles, the filter can double-up as a noise bandwidth reduction filter that can relax the digital-filtering requirements in the MCU.

Figure 12 illustrates the switched RC filter response for a sampling duty cycle of 1% across different PRF settings.

Figure 13 illustrates the switched RC filter response for a sampling duty cycle of 5% across different PRF settings.

Figure 14 illustrates the LED current value versus the LED current setting code. The mode marked as 50-mA LED Current Mode corresponds to the default setting of ILED_2X = 0, whereas the mode marked as 100-mA LED Current Mode corresponds to ILED_2X = 1. The ideal slope of these curves corresponds to 0.793 mA per code for the 50-mA current mode and 1.587 mA per code for the 100-mA current mode. However, a small deviation from these ideal values can exist from device to device, and can be viewed as a gain error in the LED current versus code. This deviation can be larger for the 100-mA current mode, with slight saturation of current especially at the high-current settings.

Figure 15 illustrates the LED current as a function of the voltage at the TX pin. The voltage at the TX pin is changed by connecting a load resistor from the TX pin to TX_SUP and changing the voltage of TX_SUP. In the 50-mA current mode, with a 50-mA current setting, the LED current starts to drop when the voltage at the TX pin goes below 0.5 V. In the 100-mA current mode, with a 100-mA current setting, the current starts to drop when the voltage at the TX pin goes below 1 V.

Figure 16 and Figure 17 illustrate the LED current step error as a function of the LED current setting code for the 50-mA and 100-mA current modes. These plots are generated from the data in Figure 14 after removing the gain error component (based on the best-fit curve).

Figure 18 illustrates the power-supply rejection ratio (PSRR) for a tone on the TX_SUP power rail. The frequency of the tone is swept and the magnitude of the same tone at the device output (LED-ambient) is monitored. Note that in cases where the tone frequency is greater than PRF / 2, power is monitored at the aliasing frequency. PSRR is computed as the RMS value of the output tone referred to the RMS value of the tone applied on the supply pin.

Figure 19 illustrates the PSRR for a tone applied on the RX_SUP power rail. PSRR is enhanced because of the presence of an internal LDO that drives the signal chain as well as the differential nature of the signal chain.

Figure 20 illustrates the rejection of a 50-Hz differential input tone. A differential current input with a frequency of 50 Hz is applied on the input pins. The magnitude of the tone at the output of the device (LED minus ambient phase) is converted to an input-referred current and compared with the magnitude of the injected current to estimate the rejection. The rejection is plotted as a function of the separation between the sampling instants of the LED and ambient phases. As illustrated in Figure 20, with reducing separation between the sampling instants, the rejection keeps improving because of an increased correlation of the injected tone between the two phases. A similar rejection is not obtained if only the LED phase data are considered.

Figure 21 illustrates the SNR in dBFS over a 20-Hz bandwidth across sampling duty cycle over multiple operating temperatures ranging from –40°C to 85°C.

Figure 22 illustrates the variation of the internal oscillator frequency over operating temperature on a typical unit.

Choosing the Right AFE Settings

The AFE signal chain offers several knobs that can be adjusted to achieve the SNR requirements needed for high-end, clinical, pulse-oximeter applications as well as for the low-power demands of battery-operated, optical, heart-rate monitoring applications. The knobs include TIA gain (Rf), TIA bandwidth, LED current (ILED), and offset cancellation DAC (I_OFFDAC). TI highly recommends running a calibration algorithm at startup and also periodically on the MCU to monitor the dc level at the output of the AFE and adjust the AFE signal chain settings to get close to the target dc level.

In addition to a target dc level, the high and low thresholds can also be determined (for example, 80% and 20% of full-scale), which can cause the algorithm to switch to a different TIA gain or LED current setting when the signal amplitude changes beyond the thresholds.

The optimum gain and LED current depends on the following conditions:

  1. The current transfer ratio (CTR) from the LED to the photodiode
  2. The perfusion index at the ADC output (the ac to dc ratio of the signal)

For clinical SPO2 applications demanding the highest SNR, where power may not be a primary concern, TI recommends setting the LED and sampling pulse durations to > 200 µs. To simplify system design, keeping the pulse duration fixed across use cases is easiest. Set the LED current to the highest value that can be afforded by the system power budget. Initialize the TIA gain to the lowest gain setting of 10 kΩ and use the initial calibration routine to determine the optimum gain. Set the ADC in averaging mode with the number of averages being the maximum afforded by the choice of pulse repetition period and pulse duration. Eight ADC averages is usually sufficient to obtain good SNR.

For power-critical, battery-operated applications, choose a sampling pulse duration between 50 µs to 100 µs and operate the device at a high TIA gain setting (for example, 1 MΩ). Set the ADC in averaging mode with four to eight averages. Initialize the LED current to the desired lowest setting (of a few milliamps) and use the initial calibration routine to determine the optimum LED current setting up to the highest value allowed by the system power budget.

For pulse-oximeter applications using red and IR LEDs, the target dc level can be typically set to 50% of positive full-scale.

For HRM applications, the offset cancellation DAC can be additionally used such that the dc offset can be subtracted from the signal, thereby allowing for a larger TIA gain to be applied without saturating the signal.

The calibration routine must be designed in a manner that does not rely on the accuracy of the LED current, TIA gain, and offset cancellation DAC, thus allowing for device-to-device variations. Specifically, the offset cancellation DAC is not trimmed at production and can have a significant device-to-device variation (±20%). If the calibration routine requires an accurate estimate of the offset cancellation DAC, then the PD_DISCONNECT mode can be used to estimate the offset cancellation DAC range on a given unit. The PD_DISCONNECT mode disconnects the photodiode from the TIA inputs. In this mode IPD = 0 and, thus, the effective input current to the TIA comes solely from the offset cancellation DAC (Ieff = I_OFFDAC). As a result, the offset cancellation DAC value can be directly estimated from the AFE output code.

When the calibration loop is in the process of converging to the steady state, the device settings can continue to be refreshed to new values. Ideally, a time equal to tCHANNEL is provided for the AFE to settle to any change in signal-chain settings. However, this time can lead to unacceptably large delays in the convergence of the calibration routine. Therefore, during the transient (when the calibration routine is in the transient phase), the wait times can be reduced to as low as tCHANNEL / 10. After the calibration routine converges to the final settings, a wait time of tCHANNEL can then be applied before high-accuracy data are read out from the AFE.