8.3.1 TIA and Switched RC Filter

The receiver input pins (INP, INM) are meant to be connected differentially to a photodiode. The signal current from the photodiode is converted to a differential voltage using a transimpedance amplifier (TIA). The TIA gain is set by its feedback resistor (R_f) and can be programmed from 10 kΩ to 2 MΩ. The transimpedance gain between the input current and output differential voltage of the TIA is equal to 2 × R_f. At the output of the TIA is a switched RC filter. There are four parallel instances of the filter, each of which are connected to the TIA output signal during one of four sampling phases.

The signal chain is kept fully differential throughout the receiver channel in order to enable excellent rejection of common-mode noise as well as noise on power supplies. For simplicity, the scheme with the four parallel filters is shown in Figure 23 for a single-ended representation of the signal chain. The ADCRST signal corresponds to the collection of active phases of four ADCRST pulses: ADCRST0, ADCRST1, ADCRST2, and ADCRST3.

NOTE: For simplicity, this circuit is shown in single-ended format.

1. ADCRST corresponds to ADCRST0, ADCRST1, ADCRST2, or ADCRST3.

Figure 23. Four Sampling and Conversion Phases Diagram

8.3.1.1 Operation with Two and Three LEDs

The four sampling phases can correspond to either of the following signal state sequences received by the photodiode:

1. 2-LED mode: LED2 → ambient phase 2 → LED1 → ambient phase 1
2. 3-LED mode: LED2 → LED3 → LED1 → ambient

The sequence of the phases within a pulse repetition cycle is shown in Figure 24.

Figure 24. Sequence of Four Sampling and Conversion Phases

In the 2-LED mode, LED1 and LED2 are pulsed during the corresponding sampling instants. In the 3-LED mode, LED1, LED2, and LED3 are pulsed during the corresponding sampling instants. As mentioned in the TIA Gain Settings and Operation with Two and Three LEDs sections, the TIA gain (R_f) and feedback capacitor (C_f) can be programmed differently between two sets: R_f1 / C_f1 and R_f2 / C_f2. The way these sets are applied to the four phases is shown in Figure 24.

8.3.1.1.1 LED Current Setting

The default LED current range is from 0 mA to 50 mA. The individual currents of each of the three LEDs can be controlled independently, each with a separate 6-bit control.

Taken as a decimal number, the 6-bit setting provides 63 equal steps between 0 mA and 50 mA. Each increment of the ILED 6-bit code causes the LED current setting to increment by approximately 0.8 mA. For details, see register 22h.

The LED current range can be doubled by setting the ILED_2X bit to 1. The accuracy of higher current settings close to 100 mA can be low because of current saturation of the driver. Each increment of the ILED 6-bit code causes the LED current to increment by approximately 1.6 mA when ILED_2X is set to 1.

8.3.2 Power Management

The AFE has three independent supplies for the transmitter, receiver, and I/O.

8.3.2.1 Transmitter Supply (TX_SUP)

The transmitter supply has a range of 3.0 V to 5.25 V. In the most common arrangement, this supply can be the same supply that the anodes of the LEDs are tied to, as shown in Figure 25.

Figure 25. LED to Pin Connections

When the LEDs must be tied to a different supply, care must be taken to ensure that the LED supply is within
0.3 V of TX_SUP. This consideration of the LED supply voltage prevents the electrostatic discharge (ESD) diodes inside the AFE from turning on during the off state of the LEDs.

8.3.3 Offset Cancellation DAC

A typical optical heart-rate signal has a dc component and an ac component. Although a higher TIA gain maximizes the ac signal at the AFE output, the magnitude of the dc component limits the maximum gain possible in the TIA. In order to decouple the affect of the dc level on the allowed ac signal gain, a current digital-to-analog converter (DAC) is placed at the input of the device. By setting a programmable cancellation current (based on the dc current signal level), the effective signal that is gained up by the TIA can be reduced. This reduction in the effective signal current into the TIA results in the ability to set a higher TIA gain than what is otherwise possible without enabling the offset correction. In each of the four phases of operation, a separate programmable current value can be set by programming four different sets of register bits. These cancellation currents are automatically presented to the input of the TIA in the appropriate phase. The ability to set a different cancellation current in each of the four phases can be used to cancel out the ambient current in the ambient phase. In the LED on phase, this ability can be used to cancel out the sum of the ambient current and dc current of the heart-rate signal. The polarities of the signal current and offset cancellation current is illustrated in Figure 26. The polarity of the offset cancellation current can be reversed by programming the POL_OFFDAC bits.

With zero input current and zero current in the offset cancellation DAC, the output of the AFE will be close to zero. Based on the channel offset, the output voltage for zero input current could be a small positive or negative value, usually in the range of several mV. With the photodiode connected as shown in Figure 26 and a signal current coming from the photodiode, the output code of the device is expected to be positive with the offset cancellation DAC set to zero (I_offset = 0). With I_offset set negative (POL_OFFFAC = 1), a dc offset can be subtracted from the signal and the ac signal can be amplified with a higher gain than what is otherwise possible.

Figure 26. Offset Cancellation Current Polarity Diagram

A breakdown of the signal current and voltage levels is provided in Table 2 for a variety of signal levels. In Table 2, the current transfer ratio (CTR) is used to describe the relationship between the set LED current and the resulting photodiode current (IPD). CTR is the ratio of the photodiode current for a given LED current and is a function of the optical and mechanical parameters as well as human physiology.

8.3.4 Analog-to-Digital Converter (ADC)

The AFE has an ADC that provides a 22-bit representation of the current from the photodiode. The ADC codes corresponding to the various sampling phases can be read out from 24-bit registers in twos complement format. The ADC full-scale input range is ±1.2 V and spans bits 21 to 0. The mapping of the ADC input voltage to the ADC code is shown in Table 3.

The two MSBs of the 24-bit word serve as sign-extension bits to the 22-bit ADC code and are equal to the MSB of the 22-bit ADC code when the input to the ADC is within its full-scale range, as shown in Table 4.

Noted that the TIA has an operating range of ±1 V even though the ADC input full-scale range is ±1.2 V, as shown in Figure 27. When setting the TIA gain, ensure that the signal at the TIA output does not exceed ±1 V.

Figure 27. TIA and ADC Dynamic Ranges

8.3.5 I²C Interface

The AFE has an I²C interface for communication. The I2C_CLK and I2C_DAT lines require external pullup resistors to IO_SUP. See the I²C protocol standards documents for details of the I²C interface. This section only describes certain key features of the interface. The data on I2C_DAT must be stable during the high level of I2C_CLK and may transition during the low level of I2C_CLK, as shown in Figure 28.

Figure 28. Allowed Transition of I2C_DAT while Transmission of Data Bits

The start condition is indicated by a high-to-low transition of the I2C_DAT line when the I2C_CLK is high. A stop condition is indicated by a low-to-high transition of the I2C_DAT line when the I2C_CLK is high. Figure 29 shows the start and stop conditions.

Figure 29. Transition of I2C_DAT during Start and Stop Conditions

With the previously mentioned protocols for data, start, and stop conditions in place, the write and read operations are as shown in Figure 30 and Figure 31, respectively. In Figure 30 and Figure 31, the slave address for the AFE (indicated as SA6 to SA0) is a 7-bit representation of address 58h. The R/W bit is the read/write bit and is set to '1' for Read and '0' for Write. Only the ADC output registers (addressed from 2Ah to 2Fh) can be read out without the need for setting the REG_READ bit. Prior to reading out any other register, the REG_READ bit needs to be additionally set to '1'. In Figure 30 and Figure 31, the activity performed by the host is shown in black whereas activity from the AFE is shown in red. Thus, after the host sends the slave address during a write operation, the AFE pulls the I2C_DAT line low (shown as ACK) if the slave address matches 58h. Similarly, the host pulls the I2C_DAT line high (shown as NACK) as acknowledgment of a successfully completed read operation involving three bytes of data. Continuous read/write mode is not supported.

1. Activity performed by the host is shown in black whereas activity from the AFE is shown in red. Continuous read/write mode is not supported.

Figure 30. I²C Write Option Timing1

Figure 31. I²C Read Option Timing1

8.3.6 Timing Engine

The AFE has a fully-integrated timing engine that can be programmed to generate all clock phases for synchronized transmit drive, receive sampling, and data conversion. To enable the timing engine (after powering up the device), enable the TIMEREN bit.

8.3.6.2 Timing Control Registers

The start and stop counts for the various dynamic signals generated by the timing engine are shown in Table 5. The timing edge numbers are in reference to Figure 32.

Table 5. Timing Register and Edge Details

TIMING SIGNAL	DESCRIPTION	REGISTER ADDRESS (Hex)	TIMING EDGE
LED2STC	Sample LED2 start	1h	TE3
LED2ENDC	Sample LED2 end	2h	TE4
LED1LEDSTC	LED1 start	3h	TE17
LED1LEDENDC	LED1 end	4h	TE18
ALED2STC\LED3STC	Sample ambient 2 (or sample LED3) start	5h	TE11
ALED2ENDC\LED3ENDC	Sample ambient 2 (or sample LED3) end	6h	TE12
LED1STC	Sample LED1 start	7h	TE19
LED1ENDC	Sample LED1 end	8h	TE20
LED2LEDSTC	LED2 start	9h	TE1
LED2LEDENDC	LED2 end	Ah	TE2
ALED1STC	Sample ambient 1 start	Bh	TE25
ALED1ENDC	Sample ambient 1 end	Ch	TE26
LED2CONVST	LED2 convert phase start	Dh	TE7
LED2CONVEND	LED2 convert phase end	Eh	TE8
ALED2CONVST\LED3CONVST	Ambient 2 (or LED3) convert phase start	Fh	TE15
ALED2CONVEND\LED3CONVEND	Ambient 2 (or LED3) convert phase end	10h	TE16
LED1CONVST	LED1 convert phase start	11h	TE23
LED1CONVEND	LED1 convert phase end	12h	TE24
ALED1CONVST	Ambient 1 convert phase start	13h	TE29
ALED1CONVEND	Ambient 1 convert phase end	14h	TE30
ADCRSTSTCT0	ADC reset phase 0 start	15h	TE5
ADCRSTENDCT0	ADC reset phase 0 end	16h	TE6
ADCRSTSTCT1	ADC reset phase 1 start	17h	TE13
ADCRSTENDCT1	ADC reset phase 1 end	18h	TE14
ADCRSTSTCT2	ADC reset phase 2 start	19h	TE21
ADCRSTENDCT2	ADC reset phase 2 end	1Ah	TE22
ADCRSTSTCT3	ADC reset phase 3 start	1Bh	TE27
ADCRSTENDCT3	ADC reset phase 3 end	1Ch	TE28

When three LEDs are used within a single period, the Ambient2 phase is replaced by the LED3 phase. The timing controls for driving the third LED are as shown in Table 6.

Table 6. Timing Controls for Driving the Third LED

TIMING SIGNAL	DESCRIPTION	REGISTER ADDRESS (Hex)	TIMING EDGE
LED3LEDSTC	LED3 start	36h	TE9
LED3LEDENDC	LED3 end	37h	TE10

The timing diagram for when all three LEDs are active is shown in Figure 32.

Figure 32. Timing Diagram

8.3.6.3 Receiver Timing

The timing engine can be programmed to set the different phases of the receiver. The relative timings of the LED phase, sampling phase, ADC reset phase, and ADC conversion phases are shown in Figure 33 and Table 7.

Figure 33. Receiver Timing Guidelines

Table 7. Receiver Timing Details

		MIN	MAX	UNIT
t1	Start of LED to start of sampling	Max [25, (0.2 × LED pulse duration)]		µs
t2	End of LED to start of ADC reset phase	2		Counts(1)
t3	Duration of ADC reset phase	6		Counts
t4	End of ADC reset phase to start of ADC conversion phase	2	2	Count
t5	Duration of ADC conversion phase(2)	(NUMAV + 2) × 200 × tADC + 15(3)		µs

(1) Refers to one clock period of CLK_TE.

(2) See Figure 36 for notations of the clocking domain.

(3) t_ADC = 1 / f_ADC.

The fourth ADCRST signal (ADCRST3) in a period also defines the start of the ADC_RDY pulse. The rising edge of the ADC_RDY signal can be used as an interrupt by the MCU to readout the registers corresponding to the preceding four conversions in that period. If any of the four conversion phases are not needed, then their duration can be set to 0. However, the corresponding ADCRSTx pulse must still be defined. All four ADCRSTx pulses must be defined in order to generate the ADC_RDY pulse. A scheme of the ADC_RDY pulse generation is shown in Figure 34. The ADC_RDY pulse timing is shown in Table 8.

Figure 34. ADC_RDY Generation Scheme

Table 8. ADC_RDY Timing Details

		TYP	MAX	UNIT
t6	End of fourth ADC reset phase to start of ADC_RDY pulse	(NUMAV + 1) × 200 × tADC	(NUMAV + 2) × 200 × tADC + 15	µs
t7	ADC_RDY pulse duration	tADC(1)		µs

(1) If a larger pulse duration is needed for the ADC_RDY interrupt, use PROG_TG_EN to enable a programmable timing signal to come out of the ADC_RDY pin. The location of the signal can be set using the PROG_TG_STC and PROG_TG_ENDC counts.

8.3.6.4 Dynamic Power-Down Timing

The dynamic power-down feature can be used to shut down the receiver inside every cycle to save power, as shown in Figure 35 and Table 9.

Figure 35. Dynamic Power-Down Timing Diagram

Table 9. Dynamic Power-Down Timing Details

		MIN	UNIT
t8	End of 4th conversion phase to the start of PDNCYCLE	200	µs
t9	End of PDNCYCLE to start of next period	200	µs

The timing controls for the PDNCYCLE pulse are shown in Table 10.

Table 10. Timing Controls for Dynamic Power-Down

TIMING SIGNAL	DESCRIPTION	REGISTER ADDRESS (Hex)	TIMING EDGE(1)
PDNCYCLESTC	Dynamic power-down start	32h	TE31
PDNCYCLEENDC	Dynamic power-down end	33h	TE32

(1) See Figure 32.

8.4.1 Power Modes

The AFE has the following power modes:

1. Normal mode.
2. Hardware power-down mode (PWDN): this mode is set using the RESETZ pin. When the RESETZ pin is pulled low for more than 200 µs, the device enters hardware power-down mode where the power consumption is very low (of a few µA).
3. Software power-down mode (PDNAFE) using a register bit.
4. Dynamic power-down mode: this mode is enabled by setting the start and end points of the PDN_CYCLE signal that is controlled using the timing engine. During the PDN_CYCLE high phase, the functional blocks (as selected by the DYNAMICx bits) are powered down. When powering down the TIA in dynamic power-down mode, consideration must be given to the dynamics of the photodiode. When the TIA is powered down, the feedback mechanism is no longer available to maintain zero bias across the photodiode, resulting in a voltage drift across the photodiode. When the AFE comes out of dynamic power-down into active mode, a transient recovery time for the photodiode results. Additionally, the INP, INM pins can be shorted through a switch to an internal reference voltage (VCM) to keep the photodiode in zero bias whenever the TIA is in power-down mode. Maintaining zero bias across the photodiode is accomplished by setting the ENABLE_INPUT_SHORT bit to 1. By setting this bit in conjunction with the DYNAMIC3 bit, the dynamics of the photodiode can be better controlled during the dynamic power-down mode.

8.4.2 RESET Modes

The AFE has internal registers that must be reset before valid operation. There are two ways to reset the device:

1. Either through the RESETZ pin (a reset signal can be issued by pulsing the RESETZ pin low for a duration of time between 25 to 50 µs) or
2. A software reset via the SW_RESET register bit.

8.4.3 Clocking Modes

The AFE has an internal oscillator that can generate a 4-MHz clock. This clock can be made to come out of the CLK pin for use by the rest of the system. The default mode is to use an external clock. The frequency range of this external clock is between 4 MHz to 60 MHz. A programmable internal division ratio between 1 to 12 must be set so that the divided clock is between 4 MHz to 6 MHz. For high-accuracy measurements, operating the AFE using an input (external) clock with high accuracy is preferable. If a high-accuracy measurement is required when using the internal oscillator, a correction scheme can be used in the MCU to digitally compensate for the inaccuracy in the oscillator. One method of this approach is to accurately estimate the PRF by measuring the ADC_RDY periodicity in terms of a high-accuracy MCU clock (for example, a 32-kHz clock) to establish the accurate PRF. This information can then be used to digitally correct the heart rate computation.

8.4.4 PRF Programmability

By default, the internal clock is 4 MHz. This clock also goes to the timing engine that has a 16-bit counter. The maximum setting of this counter (all 16 bits set to 1) determines the lowest value of PRF, resulting in a minimum PRF of 61 Hz. To extend the lower range of PRF, an independent programmable divider is introduced in the clock going to the timing engine. By programming this divider between 1 to 16 with the CLKDIV_PRF register control, the lower range of PRF can be extended from 61 Hz to approximately 4 Hz (limit the minimum PRF to
10 Hz). The various clocking domains and controls are described in Figure 36 and Table 13.

Figure 36. Clocking Domains Diagram

8.4.5 Averaging Modes

To reduce the noise, the input to the ADC (sampled on the CSAMPx capacitors) can be converted by the ADC multiple times and averaged. The number of averages is set using the NUMAV register control based on Equation 1:

By default, NUMAV = 0. Therefore, the default mode corresponds to when the ADC converts its input one time in each of the four phases and stores the content in the register corresponding to that phase.

When NUMAV is programmed (for example if NUMAV = 3), the ADC converts its input four times in each phase, averages the four conversions, and stores the averaged value in the register corresponding to that phase.

Averaging only helps in reducing ADC noise and not the front end noise because the input to the ADC is the same sampled voltage across all the ADC conversions used to generate the average (this voltage corresponds to the voltage sampled on the four CSAMPx capacitors in Figure 23). The number of samples that can be averaged ranges from 1 to 16 (when NUMAV is programmed from 0 to 15). A higher number of averages results in larger conversion times; see Table 7.

Averaging is implemented in the following manner:

The number of ADC samples corresponding to the number of averages (NUMAV + 1) are accumulated, as shown in Equation 2.

Equation 2.

where

• ADCi = the i^th sample converted by the ADC.

The accumulator output (SUMADC) is then divided by a factor D that is obtained by D = 128 ÷ X , with X being an integer.

The averaged output is shown in Equation 3:

This implementation gives an averaging function that is exact when the number of averages is a power of 2 but deviates from ideal values for other settings, as shown in Table 14.

8.4.6 Decimation Mode

The AFE4404 has a decimation mode that can be used to improve the performance at low pulse repetition frequencies (PRFs). In this mode, up to N (N = 2, 4, 8, or 16) consecutive data samples can be averaged. The averaged output comes out one time every N clock cycles. The ADC_RDY frequency also reduces to PRF / N.

A timing diagram is shown in Figure 37 for where the decimation factor = 4 and PRF = 100 Hz. Figure 37 is only intended to illustrate the change in periodicity of ADC_RDY and the update rate of the registers relative to the pulse repetition period. However, the timing of all other signals continues to be as per the descriptions mentioned in the Timing Engine section.

Figure 37. Decimation Mode Enabled Timing Diagram
(Decimation Factor = 4, PRF = 100 Hz)

Table 16. Register Map⁽¹⁾

8.5.1 Register 0h (address = 0h) [reset = 0h]

8.5.2 Register 1h (address = 1h) [reset = 0h]

8.5.3 Register 2h (address = 2h) [reset = 0h]

8.5.4 Register 3h (address = 3h) [reset = 0h]

8.5.5 Register 4h (address = 4h) [reset = 0h]

8.5.6 Register 5h (address = 5h) [reset = 0h]

8.5.7 Register 6h (address = 6h) [reset = 0h]

8.5.8 Register 7h (address = 7h) [reset = 0h]

8.5.9 Register 8h (address = 8h) [reset = 0h]

8.5.10 Register 9h (address = 9h) [reset = 0h]

8.5.11 Register Ah (address = Ah) [reset = 0h]

8.5.12 Register Bh (address = Bh) [reset = 0h]

8.5.13 Register Ch (address = Ch) [reset = 0h]

8.5.14 Register Dh (address = Dh) [reset = 0h]

8.5.15 Register Eh (address = Eh) [reset = 0h]

8.5.16 Register Fh (address = Fh) [reset = 0h]

8.5.17 Register 10h (address = 10h) [reset = 0h]

8.5.18 Register 11h (address = 11h) [reset = 0h]

8.5.19 Register 12h (address = 12h) [reset = 0h]

8.5.20 Register 13h (address = 13h) [reset = 0h]

8.5.21 Register 14h (address = 14h) [reset = 0h]

8.5.22 Register 15h (address = 15h) [reset = 0h]

8.5.23 Register 16h (address = 16h) [reset = 0h]

8.5.24 Register 17h (address = 17h) [reset = 0h]

8.5.25 Register 18h (address = 18h) [reset = 0h]

8.5.26 Register 19h (address = 19h) [reset = 0h]

8.5.27 Register 1Ah (address = 1Ah) [reset = 0h]

8.5.28 Register 1Bh (address = 1Bh) [reset = 0h]

8.5.29 Register 1Ch (address = 1Ch) [reset = 0h]

8.5.30 Register 1Dh (address = 1Dh) [reset = 0h]

8.5.31 Register 1Eh (address = 1Eh) [reset = 0h]

8.5.32 Register 20h (address = 20h) [reset = 0h]

8.5.33 Register 21h (address = 21h) [reset = 0h]

8.5.34 Register 22h (address = 22h) [reset = 0h]

8.5.35 Register 23h (address = 23h) [reset = 0h]

8.5.36 Register 29h (address = 29h) [reset = 0h]

8.5.37 Register 2Ah (address = 2Ah) [reset = 0h]

8.5.38 Register 2Bh (address = 2Bh) [reset = 0h]

8.5.39 Register 2Ch (address = 2Ch) [reset = 0h]

8.5.40 Register 2Dh (address = 2Dh) [reset = 0h]

8.5.41 Register 2Eh (address = 2Eh) [reset = 0h]

8.5.42 Register 2Fh (address = 2Fh) [reset = 0h]

8.5.43 Register 31h (address = 31h) [reset = 0h]

8.5.44 Register 32h (address = 32h) [reset = 0h]

8.5.45 Register 33h (address = 33h) [reset = 0h]