SLOSE44A October   2019  – March 2020 AFE7700

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
    1.     AFE7700 Block Diagram
  4. 4Description (continued)
  5. 5Revision History
  6. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Support Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  7. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Quad transmitters based on direct up-conversion architecture:
    • Up to 600 MHz of RF transmitted bandwidth per chain
  • Quad receivers based on 0-IF down-conversion architecture:
    • Up to 200 MHz of RF received bandwidth per chain
  • Feedback chain based on RF sampling ADC:
    • Up to 600 MHz of RF received bandwidth
  • RF frequency range: 600 MHz to 6 GHz
  • Four wideband fractional-N PLL, VCO for TX and RX LO
  • Dedicated integer-N PLL, VCO for data converters clock generation
  • JESD204B and JESD204C SerDes interface support:
    • 8 SerDes transceivers up to 29.5 Gbps
    • 8b/10b and 64b/66b encoding
    • 16-bit, 12-bit, 24-bit and 32-bit formatting
    • Subclass 1 multi-device synchronization
  • Package: 17-mm × 17-mm FCBGA, 0.8-mm pitch