SBASAF7D January   2022  – May 2025 AFE7906

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Specifications
    1. 4.1  Absolute Maximum Ratings
    2. 4.2  ESD Ratings
    3. 4.3  Recommended Operating Conditions
    4. 4.4  Thermal Information
    5. 4.5  RF ADC Electrical Characteristics
    6. 4.6  PLL/VCO/Clock Electrical Characteristics
    7. 4.7  Digital Electrical Characteristics
    8. 4.8  Power Supply Electrical Characteristics
    9. 4.9  Timing Requirements
    10. 4.10 Switching Characteristics
    11. 4.11 Typical Characteristics
      1. 4.11.1 RX Typical Characteristics 30 MHz and 400 MHz
      2. 4.11.2 RX Typical Characteristics at 800MHz
      3. 4.11.3 RX Typical Characteristics 1.75GHz to 1.9GHz
      4. 4.11.4 RX Typical Characteristics 2.6GHz
      5. 4.11.5 RX Typical Characteristics 3.5GHz
      6. 4.11.6 RX Typical Characteristics 4.9GHz
      7. 4.11.7 RX Typical Characteristics 6.8GHz
      8. 4.11.8 PLL and Clock Typical Characteristics
  6. 5Device and Documentation Support
    1. 5.1 Receiving Notification of Documentation Updates
    2. 5.2 Support Resources
    3. 5.3 Trademarks
    4. 5.4 Electrostatic Discharge Caution
    5. 5.5 Glossary
  7. 6Revision History
  8. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Description

The AFE7906 is a high performance, wide bandwidth multi-channel receiver, integrating six RF Sampling ADCs. With operation up to 12GHz, this device enables direct RF sampling in the L, S, C and X-band frequency ranges without the need for additional frequency conversions stages. This improvement in density and flexibility enables high-channel-count, multi-mission systems.

Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter). Four receiver channels have an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200MHz for four RX or 600MHz.

The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.

Each receiver chain includes a 25dB range DSA (Digital Step Attenuator), followed by a 3GSPS ADC (analog-to-digital converter). Each receiver channel has an analog peak power detector and various digital power detectors to assist an external or internal autonomous automatic gain controller, and RF overload detectors for device reliability protection. Flexible decimation options provide optimization of data bandwidth up to 1200MHz for four RX without FB paths or 600MHz with two FB paths (1200MHz BW each).

The device contains a SYSREF timing detector to allow optimization of the SYSREF input timing relative to the device clock.

Package Information
PART NUMBERPACKAGE(1)PACKAGE SIZE(2)
AFE7906FC-BGA17mm × 17mm
For all available packages, see the orderable addendum at the end of the data sheet.
The package size (length × width) is a nominal value and includes pins, where applicable.
AFE7906 Functional Block Diagram Functional Block Diagram