SLVSKO8B
December 2025 – September 2026
AWR2188
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Functional Block Diagram
5
Device and Documentation Support
5.1
Device Nomenclature
5.2
Tools and Software
5.3
Documentation support
5.4
Support Resources
5.5
Trademarks
5.6
Electrostatic Discharge Caution
5.7
Glossary
6
Revision History
7
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
APE|573
MPBGB55A
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slvsko8b_oa
1
Features
FMCW transceiver
Integrated PLL, transmitter, receiver, baseband, and ADC
76-81GHz operation with up to 4.5GHz continuous chirp bandwidth
Eight receive channels
Eight transmit channels
Ultra-accurate chirp engine based on Fractional-N PLL
TX power: 13dBm
RX noise figure: 11dB
Supports P1dB up to -6.5dBm
Industry leading 8 transmitter, 8 receiver radar front end with 2.8W power consumption
Supports less than 3 μs chirp idle time for excellent max velocity measurements
Maximum chirp slope of 266MHz/μs to enable rapid high-bandwidth measurements
ADC Sample rate up to 66.67 Msps for exceptional instrumentation range distance
Built-in calibration and self-test
Built-in firmware (ROM)
Self-calibrating system across process and temperature
Host interface
Control interface with external processor over SPI or I2C interface
Data interface with external processor over MIPI D-PHY and CSI2 v1.2
Interrupts for Fault Reporting
Functional Safety-Compliant targeted
Developed for functional safety applications
Documentation available to aid ISO 26262 functional safety system design
Systematic capability up to ASIL-D targeted
Hardware capability up to ASIL-B targeted
Safety-related certification
ISO 26262 certification by TUV planned
AEC-Q100 Targeted
AWR2188 advanced features
Embedded self-monitoring with limited Host processor involvement
Option of cascading multiple devices to increase channel count
Embedded interference detection capability
Power management
Built-in LDO Network for enhanced PSRR
I/Os support dual voltage 3.3V/1.8V
Clock source
Supports externally driven clock (square/sine) at 50 MHz or 40 MHz
Supports 50 MHz or 40 MHz crystal connection with load capacitors
Easy hardware design
Production proven innovative Launch on Package (LOP) technology with easy to route launcher positions
0.5mm pitch 14mm × 15mm FCCSP package for easy assembly and low-cost PCB design
Small solution size
Operating Conditions
Junction temp range: –40°C to 140°C, and –40°C to 142°C in TX module