SLUSBP6D september 2013 – april 2023 BQ24296 , BQ24297
PRODUCTION DATA
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Register Reset | I2C Watchdog Timer Reset | OTG_CONFIG | CHG_CONFIG | SYS_MIN[2] | SYS_MIN[1] | SYS_MIN[0] | BOOST_LIM |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write |
BIT | FIELD | TYPE | RESET | DESCRIPTION | NOTE |
---|---|---|---|---|---|
Bit 7 | Register Reset | R/W | 0 | 0 – Keep current register setting, 1 – Reset to default | Default: Keep current register setting (0) Note: Register Reset bit does not reset device to default mode |
Bit 6 | I2C Watchdog Timer Reset | R/W | 0 | 0 – Normal ; 1 – Reset | Default: Normal (0) Note: Consecutive I2C watchdog timer reset requires minimum 20-µs delay |
Charger Configuration | |||||
Bit 5 | OTG_CONFIG | R/W | 0 | 0 – OTG Disable; 1 – OTG Enable(1) | Default: OTG disable (0) Note: OTG_CONFIG would over-ride Charge Enable Function in CHG_CONFIG |
Bit 4 | CHG_CONFIG | R/W | 1 | 0- Charge Disable; 1- Charge Enable(1) | Default: Charge Battery (1) |
Minimum System Voltage Limit | |||||
Bit 3 | SYS_MIN[2] | R/W | 1 | 0.4 V | Offset: 3.0 V, Range 3.0 V – 3.7 V Default: 3.5 V (101) |
Bit 2 | SYS_MIN[1] | R/W | 0 | 0.2 V | |
Bit 1 | SYS_MIN[0] | R/W | 1 | 0.1 V | |
Boost Mode Current Limit | |||||
Bit 0 | BOOST_LIM | R/W | 1 | 0 – 1 A, 1 – 1.5 A | Default: 1.5 A (1) |