SLUSE64 May   2021 BQ25723

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Power-Up Sequence
      2. 9.3.2  Vmin Active Protection (VAP) with Battery only
      3. 9.3.3  Two-Level Battery Discharge Current Limit
      4. 9.3.4  Fast Role Swap Feature
      5. 9.3.5  CHRG_OK Indicator
      6. 9.3.6  Input and Charge Current Sensing
      7. 9.3.7  Input Voltage and Current Limit Setup
      8. 9.3.8  Battery Cell Configuration
      9. 9.3.9  Device HIZ State
      10. 9.3.10 USB On-The-Go (OTG)
      11. 9.3.11 Converter Operation
      12. 9.3.12 Inductance Detection Through IADPT Pin
      13. 9.3.13 Converter Compensation
      14. 9.3.14 Continuous Conduction Mode (CCM)
      15. 9.3.15 Pulse Frequency Modulation (PFM)
      16. 9.3.16 Switching Frequency and Dithering Feature
      17. 9.3.17 Current and Power Monitor
        1. 9.3.17.1 High-Accuracy Current Sense Amplifier (IADPT and IBAT)
        2. 9.3.17.2 High-Accuracy Power Sense Amplifier (PSYS)
      18. 9.3.18 Input Source Dynamic Power Management
      19. 9.3.19 Input Current Optimizer (ICO)
      20. 9.3.20 Two-Level Adapter Current Limit (Peak Power Mode)
      21. 9.3.21 Processor Hot Indication
        1. 9.3.21.1 PROCHOT During Low Power Mode
        2. 9.3.21.2 PROCHOT Status
      22. 9.3.22 Device Protection
        1. 9.3.22.1 Watchdog Timer
        2. 9.3.22.2 Input Overvoltage Protection (ACOV)
        3. 9.3.22.3 Input Overcurrent Protection (ACOC)
        4. 9.3.22.4 System Overvoltage Protection (SYSOVP)
        5. 9.3.22.5 Battery Overvoltage Protection (BATOVP)
        6. 9.3.22.6 Battery Discharge Overcurrent Protection (BATOC)
        7. 9.3.22.7 Battery Short Protection (BATSP)
        8. 9.3.22.8 System Undervoltage Lockout (VSYS_UVP) and Hiccup Mode
        9. 9.3.22.9 Thermal Shutdown (TSHUT)
    4. 9.4 Device Functional Modes
      1. 9.4.1 Forward Mode
        1. 9.4.1.1 System Voltage Regulation with Narrow VDC Architecture
        2. 9.4.1.2 Battery Charging
      2. 9.4.2 USB On-The-Go
      3. 9.4.3 Pass Through Mode (PTM)-Patented Technology
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Interface
        1. 9.5.1.1 Timing Diagrams
        2. 9.5.1.2 Data Validity
        3. 9.5.1.3 START and STOP Conditions
        4. 9.5.1.4 Byte Format
        5. 9.5.1.5 Acknowledge (ACK) and Not Acknowledge (NACK)
        6. 9.5.1.6 Target Address and Data Direction Bit
        7. 9.5.1.7 Single Read and Write
        8. 9.5.1.8 Multi-Read and Multi-Write
        9. 9.5.1.9 Write 2-Byte I2C Commands
    6. 9.6 Register Map
      1. 9.6.1  ChargeOption0 Register (I2C address = 01/00h) [reset = E70Eh]
      2. 9.6.2  ChargeCurrent Register (I2C address = 03/02h) [reset = 0000h]
        1. 9.6.2.1 Battery Pre-Charge Current Clamp
      3. 9.6.3  ChargeVoltage Register (I2C address = 05/04h) [reset value based on CELL_BATPRESZ pin setting]
      4. 9.6.4  ChargerStatus Register (I2C address = 21/20h) [reset = 0000h]
      5. 9.6.5  ProchotStatus Register (I2C address = 23/22h) [reset = B800h]
      6. 9.6.6  IIN_DPM Register (I2C address = 25/24h) [reset = 4100h]
      7. 9.6.7  ADCVBUS/PSYS Register (I2C address = 27/26h)
      8. 9.6.8  ADCIBAT Register (I2C address = 29/28h)
      9. 9.6.9  ADCIIN/CMPIN Register (I2C address = 2B/2Ah)
      10. 9.6.10 ADCVSYS/VBAT Register (I2C address = 2D/2Ch)
      11. 9.6.11 ChargeOption1 Register (I2C address = 31/30h) [reset = 3300h]
      12. 9.6.12 ChargeOption2 Register (I2C address = 33/32h) [reset = 00B7]
      13. 9.6.13 ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]
      14. 9.6.14 ProchotOption0 Register (I2C address = 37/36h) [reset = 4A81h(2S~4s) 4A09(1S)]
      15. 9.6.15 ProchotOption1 Register (I2C address = 39/38h) [reset = 41A0h]
      16. 9.6.16 ADCOption Register (I2C address = 3B/3Ah) [reset = 2000h]
      17. 9.6.17 ChargeOption4 Register (I2C address = 3D/3Ch) [reset = 0048h]
      18. 9.6.18 Vmin Active Protection Register (I2C address = 3F/3Eh) [reset = 006Ch(2s~4s)/0004h(1S)]
      19. 9.6.19 OTGVoltage Register (I2C address = 07/06h) [reset = 09C4h]
      20. 9.6.20 OTGCurrent Register (I2C address = 09/08h) [reset = 3C00h]
      21. 9.6.21 InputVoltage(VINDPM) Register (I2C address = 0B/0Ah) [reset =VBUS-1.28V]
      22. 9.6.22 VSYS_MIN Register (I2C address = 0D/0Ch) [reset value based on CELL_BATPRESZ pin setting]
      23. 9.6.23 IIN_HOST Register (I2C address = 0F/0Eh) [reset = 4100h]
      24. 9.6.24 ID Registers
        1. 9.6.24.1 ManufactureID Register (I2C address = 2Eh) [reset = 40h]
        2. 9.6.24.2 Device ID (DeviceAddress) Register (I2C address = 2Fh) [reset = E0h]
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 ACP-ACN Input Filter
        2. 10.2.2.2 Inductor Selection
        3. 10.2.2.3 Input Capacitor
        4. 10.2.2.4 Output Capacitor
        5. 10.2.2.5 Power MOSFETs Selection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
      1. 12.2.1 Layout Example Reference Top View
      2. 12.2.2 Inner Layer Layout and Routing Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Support Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.6.13 ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]

Figure 9-28 ChargeOption3 Register (I2C address = 35/34h) [reset = 0434h]
7 6 5 4 3 2 1 0
EN_HIZ RESET_REG RESET_VINDPM EN_OTG EN_ICO_MODE EN_PORT_CTRL EN_VSYS_MIN_SOFT_SR EN_OTG_BIGCAP
R/W R/W R/W R/W R/W R/W R/W R/W
7 6 5 4 3 2 1 0
BATFET_ENZ EN_VBUS_VAP OTG_VAP_MODE IL_AVG CMP_EN BATFETOFF_HIZ PSYS_OTG_IDCHG
R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 9-32 ChargeOption3 Register (I2C address = 35h) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 EN_HIZ R/W 0b

Device HIZ Mode Enable

When the charger is in HIZ mode, the device draws minimal quiescent current. With VBUS above UVLO. REGN LDO stays on, and system powers from battery.

0b: Device not in HIZ mode <default at POR>

1b: Device in HIZ mode
6 RESET_REG R/W 0b

Reset Registers

All the registers are reset to POR default setting except the VINDPM register.

0b: Idle <default at POR>

1b: Reset all the registers to default values. After reset, this bit goes back to 0.
5 RESET_VINDPM R/W 0b

Reset VINDPM Threshold

0b: Idle

1b: Converter is disabled to measure VINDPM threshold. After VINDPM measurement is done, this bit goes back to 0 and converter starts. (When battery voltage is lower than VSYS_MIN this function is not recommended due to potential risk to crash system during VINDPM measurement .)

4 EN_OTG R/W 0b

OTG Mode Enable

Enable device in OTG mode when OTG/VAP/FRS pin is HIGH.

0b: Disable OTG <default at POR>

1b: Enable OTG mode to supply VBUS from battery.
3 EN_ICO_MODE R/W 0b

Enable ICO Algorithm

0b: Disable ICO algorithm. <default at POR>

1b: Enable ICO algorithm.
2 EN_PORT_CTRL R/W 1b

Enable BATFET control

0b: Disable BATFET control pin by HIZ BATDRV pin

1b: Enable BATFET control pin by activate BATDRV pin
1 EN_VSYS_MIN_SOFT_SR R/W 0b Enable VSYS_MIN soft slew rate transition

0b: Disable VSYS_MIN soft slew rate transition <default at POR>

1b:Enable VSYS_MIN soft slew rate transition (1LSB/8μs=12.5mV/μs)
0 EN_OTG_BIGCAP R/W 0b

Enable OTG compensation for VBUS effective capacitance larger than 33 μF

0b: Disable OTG large VBUS capacitance compensation (Recommended for VBUS effective capacitance smaller than 33 μF) <default at POR>

1b: Enable OTG large VBUS capacitance compensation (Recommended for VBUS effective capacitance larger than 33 μF)
Table 9-33 ChargeOption3 Register (I2C address = 34h) Field Descriptions
BIT FIELD TYPE RESET DESCRIPTION
7 BATFET_ENZ R/W 0b Turn off BATFET under battery only mode. If charger is not in battery only mode this bit is not allowed to be written to 1. Under battery only OTG mode, this bit is forced to be 0b.

0b: Not force turn off BATFET <default at POR>

1b: Force turn off BATFET
6 EN_VBUS_VAP R/W 0b

Enable the VBUS VAP for VAP operation mode 2&3

0b: Disabled <default at POR>

1b: Enabled
5 OTG_VAP_MODE R/W 1b

The selection of the external OTG/VAP/FRS pin control. Don't recommend to change pin control after OTG/VAP/FRS pin is pulled high.

0b: the external OTG/VAP/FRS pin controls the EN/DIS VAP mode

1b: the external OTG/VAP/FRS pin controls the EN/DIS OTG mode <default at POR>
4-3 IL_AVG R/W 10b

Converter inductor average current clamp. It is recommended to choose the smallest option which is higher than maximum possible converter average inductor current.

00b: 6A

01b: 10A

10b: 15A <default at POR>

11b: Disabled

2 CMP_EN R/W 1b

Enable Independent Comparator with effective low.

0b: Disabled

1b: Enabled <default at POR>
1 BATFETOFF_HIZ R/W 0b

Control BATFET on/off during charger HIZ mode.

0b: BATFET on during charger HIZ mode <default at POR>

1b: BATFET off during charger HIZ mode
0 PSYS_OTG_IDCHG R/W 0b

PSYS function during OTG mode.

0b: PSYS as battery discharge power minus OTG output power <default at POR>

1b: PSYS as battery discharge power only