SLUSCH6B March   2016  – March 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Device Power-On-Reset (POR)
      2. 8.2.2  Device Power Up from Battery without Input Source
      3. 8.2.3  Device Power Up from Input Source
        1. 8.2.3.1 Power Up REGN Regulation (LDO)
        2. 8.2.3.2 Poor Source Qualification
        3. 8.2.3.3 Input Source Type Detection
          1. 8.2.3.3.1 PSEL Pin Sets Input Current Limit
          2. 8.2.3.3.2 Force Input Current Limit Detection
        4. 8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.2.3.5 Converter Power-Up
      4. 8.2.4  Power Path Management
        1. 8.2.4.1 Dynamic Power Management
      5. 8.2.5  Battery Charging Management
        1. 8.2.5.1 Autonomous Charging Cycle
        2. 8.2.5.2 Battery Charging Profile
        3. 8.2.5.3 Charging Termination
        4. 8.2.5.4 Charging Safety Timer
      6. 8.2.6  Battery Monitor
      7. 8.2.7  Status Outputs (PG, STAT, and INT)
        1. 8.2.7.1 Power Good Indicator (PG)
        2. 8.2.7.2 Charging Status Indicator (STAT)
        3. 8.2.7.3 Interrupt to Host (INT)
      8. 8.2.8  Thermal Regulation and Thermal Shutdown
        1. 8.2.8.1 Thermal Protection in Buck Mode
      9. 8.2.9  Voltage and Current Monitoring in Buck
        1. 8.2.9.1 Voltage and Current Monitoring in Buck Mode
          1. 8.2.9.1.1 Input Overvoltage (ACOV)
          2. 8.2.9.1.2 System Overvoltage Protection (SYSOVP)
      10. 8.2.10 Battery Protection
        1. 8.2.10.1 Battery Overvoltage Protection (BATOVP)
        2. 8.2.10.2 Battery Over-Discharge Protection
      11. 8.2.11 Serial Interface
        1. 8.2.11.1 Data Validity
        2. 8.2.11.2 START and STOP Conditions
        3. 8.2.11.3 Byte Format
        4. 8.2.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.2.11.5 Slave Address and Data Direction Bit
        6. 8.2.11.6 Single Read and Write
        7. 8.2.11.7 Multi-Read and Multi-Write
    3. 8.3 Device Functional Modes
      1. 8.3.1 Host Mode and Default Mode
    4. 8.4 Register Map
      1. 8.4.1  REG00
      2. 8.4.2  REG01
      3. 8.4.3  REG02
      4. 8.4.4  REG03
      5. 8.4.5  REG04
      6. 8.4.6  REG05
      7. 8.4.7  REG06
      8. 8.4.8  REG07
      9. 8.4.9  REG08
      10. 8.4.10 REG09
      11. 8.4.11 REG0A
      12. 8.4.12 REG0B
      13. 8.4.13 REG0C
      14. 8.4.14 REG0D
      15. 8.4.15 REG0E
      16. 8.4.16 REG0F
      17. 8.4.17 REG11
      18. 8.4.18 REG12
      19. 8.4.19 REG13
      20. 8.4.20 REG14
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Diagram
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Buck Input Capacitor
        3. 9.2.2.3 System Output Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

A typical application consists of the device configured as an I2C controlled power path management device and a single cell battery charger for Li-Ion and Li-polymer batteries used in a wide range of smartphones and other portable devices. It integrates an input reverse-block FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and BATFET (Q4) between the system and battery. The device also integrates a bootstrap diode for the high-side gate drive.

9.2 Typical Application Diagram

bq25898C typ_app_diag_slusch6.gif
VREF is the pull up voltage of I2C communication interface
Figure 40. bq25898C Application Diagram as Slave Charger

9.2.1 Design Requirements

For this design example, use the parameters shown in Table 26.

Table 26. Design Parameters

PARAMETER VALUE
Input voltage range 3.9 V to 14 V
Input current limit 1.5 A
Fast charge current 3000 mA
Output voltage 4.208 V

9.2.2 Detailed Design Procedure

9.2.2.1 Inductor Selection

The device has 1.5 MHz switching frequency to allow the use of small inductor and capacitor values. The Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):

Equation 1. bq25898C eq3_Ibat_slusbu7.gif

The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VVBUS), switching frequency (fs) and inductance (L):

Equation 2. bq25898C eq4_Iripple_slusbu7.gif

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design.

9.2.2.2 Buck Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current IPMID occurs where the duty cycle is closest to 50% and can be estimated by Equation 3:

Equation 3. bq25898C eq5_Icin_slusbu7.gif

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25 V rating or higher capacitor is preferred for up to 14-V input voltage. 8.2-μF capacitance is suggested.

9.2.2.3 System Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current ICOUT is given:

Equation 4. bq25898C eq6_Icout_slusbu7.gif

The output capacitor voltage ripple can be calculated as follows:

Equation 5. bq25898C eq7_Vout_slusbu7.gif

At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC. The charger device has internal loop compensator. To get good loop stability, 1-µH and minimum of 20-µF output capacitor is recommended. The preferred ceramic capacitor is 6V or higher rating, X7R or X5R.

9.2.3 Application Curves

bq25898C tek00072_Fig50_slusca6.png
VBAT = 3.2 V, VBUS = 5 V
Figure 41. Power Up with Charge Disabled
bq25898C tek00079_FIG52_slusca6.png
VBUS = 5 V
Figure 43. Charge Enable
bq25898C tek00096_FIG56_slusca6.png
VBUS = 12 V VBAT = 3.8 V ICHG = 3 A
Figure 45. PWM Switching Waveform
bq25898C tek00082_FIG60_slusca6.png
VBAT = 3.2 V VBUS = 12 V
Figure 47. Power Up with Charge Disabled
bq25898C tek00081_FIG62_slusca6.png
VBUS = 12 V
Figure 49. Charge Disable
bq25898C tek00073_FIG51_slusca6.png
VBAT = 3.2 V, VBUS = 5 V
Figure 42. Power Up with Charge Enabled
bq25898C tek00076_FIG53_slusca6.png
VBUS = 5 V
Figure 44. Charge Disable
bq25898C tek00102_FIG57_slusca6.png
VBUS = 9V ISYS = 20 mA, Charge Disable
No Battery
Figure 46. PFM Switching Waveform
bq25898C tek00080_FIG61_slusca6.png
VBUS = 12 V
Figure 48. Charge Enable
bq25898C tek00086_FIG63_slusca6.png
VBUS = 12 V VBAT = 3.8 V ICHG = 3 A
Figure 50. PWM Switching Waveform