SLUSCH6B March   2016  – March 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Device Power-On-Reset (POR)
      2. 8.2.2  Device Power Up from Battery without Input Source
      3. 8.2.3  Device Power Up from Input Source
        1. 8.2.3.1 Power Up REGN Regulation (LDO)
        2. 8.2.3.2 Poor Source Qualification
        3. 8.2.3.3 Input Source Type Detection
          1. 8.2.3.3.1 PSEL Pin Sets Input Current Limit
          2. 8.2.3.3.2 Force Input Current Limit Detection
        4. 8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.2.3.5 Converter Power-Up
      4. 8.2.4  Power Path Management
        1. 8.2.4.1 Dynamic Power Management
      5. 8.2.5  Battery Charging Management
        1. 8.2.5.1 Autonomous Charging Cycle
        2. 8.2.5.2 Battery Charging Profile
        3. 8.2.5.3 Charging Termination
        4. 8.2.5.4 Charging Safety Timer
      6. 8.2.6  Battery Monitor
      7. 8.2.7  Status Outputs (PG, STAT, and INT)
        1. 8.2.7.1 Power Good Indicator (PG)
        2. 8.2.7.2 Charging Status Indicator (STAT)
        3. 8.2.7.3 Interrupt to Host (INT)
      8. 8.2.8  Thermal Regulation and Thermal Shutdown
        1. 8.2.8.1 Thermal Protection in Buck Mode
      9. 8.2.9  Voltage and Current Monitoring in Buck
        1. 8.2.9.1 Voltage and Current Monitoring in Buck Mode
          1. 8.2.9.1.1 Input Overvoltage (ACOV)
          2. 8.2.9.1.2 System Overvoltage Protection (SYSOVP)
      10. 8.2.10 Battery Protection
        1. 8.2.10.1 Battery Overvoltage Protection (BATOVP)
        2. 8.2.10.2 Battery Over-Discharge Protection
      11. 8.2.11 Serial Interface
        1. 8.2.11.1 Data Validity
        2. 8.2.11.2 START and STOP Conditions
        3. 8.2.11.3 Byte Format
        4. 8.2.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.2.11.5 Slave Address and Data Direction Bit
        6. 8.2.11.6 Single Read and Write
        7. 8.2.11.7 Multi-Read and Multi-Write
    3. 8.3 Device Functional Modes
      1. 8.3.1 Host Mode and Default Mode
    4. 8.4 Register Map
      1. 8.4.1  REG00
      2. 8.4.2  REG01
      3. 8.4.3  REG02
      4. 8.4.4  REG03
      5. 8.4.5  REG04
      6. 8.4.6  REG05
      7. 8.4.7  REG06
      8. 8.4.8  REG07
      9. 8.4.9  REG08
      10. 8.4.10 REG09
      11. 8.4.11 REG0A
      12. 8.4.12 REG0B
      13. 8.4.13 REG0C
      14. 8.4.14 REG0D
      15. 8.4.15 REG0E
      16. 8.4.16 REG0F
      17. 8.4.17 REG11
      18. 8.4.18 REG12
      19. 8.4.19 REG13
      20. 8.4.20 REG14
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Diagram
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Buck Input Capacitor
        3. 9.2.2.3 System Output Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the components to minimize high frequency current path loop (see Figure 51) is important to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout priority list for proper layout. Layout PCB according to this specific order is essential.

  1. Place input capacitor as close as possible to PMID pin and GND pin connections and use shortest copper trace connection or GND plane.
  2. Put output capacitor near to the inductor and the IC.
  3. Decoupling capacitors should be placed next to the IC pins and make trace connection as short as possible.
  4. Place inductor input terminal to SW pin as close as possible. Minimize the copper area of this trace to lower electrical and magnetic field radiation but make the trace wide enough to carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic capacitance from this area to any other trace or plane.
  5. Connect all grounds together to reduce PCB size and improve thermal dissipation.
  6. Avoid ground planes in parallel with high frequency traces in other layers.

11.2 Layout Example

bq25898C High_Frequency_Current_Path_SLUSAW5.gif Figure 51. High Frequency Current Path