7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER |
MIN |
MAX |
UNIT |
VBAT |
BAT pin input voltage range |
–0.3 |
6 |
V |
VDD |
VDD pin supply voltage range (LDO output) |
–0.3 |
2 |
V |
VIOD |
Open-drain I/O pins (SDA, SCL, GPOUT) |
–0.3 |
6 |
V |
VIOPP |
Push-Pull I/O pins (BIN) |
–0.3 |
[VDD + 0.3] |
V |
TA |
Operating free-air temperature range |
–40 |
85 |
°C |
Tstg |
Storage temperature |
–65 |
150 |
°C |
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
|
VALUE |
UNIT |
V(ESD) |
Electrostatic discharge |
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) |
±1000 |
V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) |
±250 |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
TA = 30°C and VREGIN = VBAT = 3.6 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
NOM |
MAX |
UNIT |
CBAT(1) |
Optional external input capacitor for internal LDO between BAT and VSS |
Nominal capacitor values specified. Recommend a 5% ceramic X5R type capacitor located close to the device. |
|
0.1 |
|
μF |
CLDO18 (1) |
External output capacitor for internal LDO between VDD and VSS |
|
0.47 |
|
μF |
VPU (1) |
External pullup voltage for open-drain pins (SDA, SCL, GPOUT) |
|
1.62 |
|
3.6 |
V |
(1) Specified by design. Not production tested.
7.4 Thermal Information
THERMAL METRIC(1) |
bq27621-G1 |
UNIT |
YZF (DSBGA) |
9 PINS |
RθJA |
Junction-to-ambient thermal resistance |
107.8 |
°C/W |
RθJC(top) |
Junction-to-case (top) thermal resistance |
0.7 |
°C/W |
RθJB |
Junction-to-board thermal resistance |
60.4 |
°C/W |
ψJT |
Junction-to-top characterization parameter |
3.5 |
°C/W |
ψJB |
Junction-to-board characterization parameter |
60.4 |
°C/W |
RθJC(bot) |
Junction-to-case (bottom) thermal resistance |
n/a |
°C/W |
(1) For more information about traditional and new thermal metrics, see the
IC Package Thermal Metrics Application Report,
SPRA953.
7.5 Supply Current
TA = 30°C and VREGIN = VBAT = 3.6 V (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
ICC (1) |
NORMAL mode current |
ILOAD > Sleep Current |
|
27 |
|
μA |
ISLP (1) |
SLEEP mode current |
ILOAD < Sleep Current |
|
21 |
|
μA |
IHIB (1) |
HIBERNATE mode current |
ILOAD < Hibernate Current |
|
9 |
|
μA |
ISD (1) |
SHUTDOWN mode current |
Fuel gauge in host commanded SHUTDOWN mode. (LDO Regulator Output Disabled) |
|
0.6 |
|
μA |
(1) Specified by design. Not production tested.
7.6 Digital Input and Output DC Characteristics
TA = –40°C to 85°C, typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(Force Note1)(1)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VIH(OD) |
Input voltage, high (2) |
External pullup resistor to VPU |
VPU × 0.7 |
|
|
V |
VIL |
Input voltage, low (2) (3) |
|
|
|
0.6 |
V |
VOL |
Output voltage, low (2) |
|
|
|
0.6 |
V |
IOH |
Output source current, high (2) |
|
|
|
0.5 |
mA |
IOL(OD) |
Output sink current, low (2) |
|
|
|
–3 |
mA |
CIN (1) |
Input capacitance (2) (3) |
|
|
|
5 |
pF |
Ilkg |
Input leakage current (SCL, SDA, BIN) |
|
|
|
0.1 |
μA |
Input leakage current (GPOUT) |
|
|
1 |
(1) Specified by design. Not production tested.
(2) Open drain pins: (SCL, SDA, GPOUT)
(3) Push-pull pin: (BIN)
7.7 LDO Regulator, Wake-up, and Auto-Shutdown DC Characteristics
TA = –40°C to 85°C, typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted)(Force Note1)(1)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VBAT |
BAT pin regulator input |
|
2.45 |
|
4.5 |
V |
VDD |
Regulator output voltage |
|
|
1.8 |
|
V |
UVLOIT+ |
VBAT Undervoltage Lock Out LDO Wake-Up Rising Threshold |
|
|
2 |
|
V |
UVLOIT– |
VBAT Undervoltage Lock Out LDO Auto-Shutdown Falling Threshold |
|
|
1.95 |
|
V |
(1) Specified by design. Not production tested.
7.8 ADC (Temperature and Cell Measurement) Characteristics
TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted) (Force Note1)(1)
PARAMETER |
TEST CONDITIONS |
MIN |
TYP |
MAX |
UNIT |
VIN(BAT) |
BAT pin voltage measurement range. |
Voltage divider enabled. |
2.45 |
|
4.5 |
V |
tADC_CONV |
Conversion time |
|
|
125 |
|
ms |
|
Effective Resolution |
|
|
15 |
|
bits |
(1) Specified by design. Not tested in production.
7.9 I2C-Compatible Interface Communication Timing Characteristics
TA = –40°C to 85°C; typical values at TA = 30°C and VREGIN = 3.6 V (unless otherwise noted) (Force Note1)(1)
PARAMETER |
TEST CONDITIONS |
|
MIN |
NOM |
MAX |
UNIT |
Standard Mode (100 kHz) |
td(STA) |
Start to first falling edge of SCL |
|
|
4 |
|
|
µs |
tw(L) |
SCL pulse duration (low) |
|
|
4.7 |
|
|
µs |
tw(H) |
SCL pulse duration (high) |
|
|
4 |
|
|
µs |
tsu(STA) |
Setup for repeated start |
|
|
4.7 |
|
|
µs |
tsu(DAT) |
Data setup time |
Host drives SDA |
|
250 |
|
|
ns |
th(DAT) |
Data hold time |
Host drives SDA |
|
0 |
|
|
ns |
tsu(STOP) |
Setup time for stop |
|
|
4 |
|
|
µs |
t(BUF) |
Bus free time between stop and start |
Includes Command Waiting Time |
|
66 |
|
|
µs |
tf |
SCL/SDA fall time (1) |
|
|
|
|
300 |
ns |
tr |
SCL/SDA rise time (1) |
|
|
|
|
300 |
ns |
fSCL |
Clock frequency(2) |
|
|
|
|
100 |
kHz |
Fast Mode (400 kHz) |
td(STA) |
Start to first falling edge of SCL |
|
|
600 |
|
|
ns |
tw(L) |
SCL pulse duration (low) |
|
|
1300 |
|
|
ns |
tw(H) |
SCL pulse duration (high) |
|
|
600 |
|
|
ns |
tsu(STA) |
Setup for repeated start |
|
|
600 |
|
|
ns |
tsu(DAT) |
Data setup time |
Host drives SDA |
|
100 |
|
|
ns |
th(DAT) |
Data hold time |
Host drives SDA |
|
0 |
|
|
ns |
tsu(STOP) |
Setup time for stop |
|
|
600 |
|
|
ns |
t(BUF) |
Bus free time between stop and start |
Includes Command Waiting Time |
|
66 |
|
|
µs |
tf |
SCL/SDA fall time (1) |
|
|
|
|
300 |
ns |
tr |
SCL/SDA rise time (1) |
|
|
|
|
300 |
ns |
fSCL |
Clock frequency(2) |
|
|
|
|
400 |
kHz |
(1) Specified by design. Not production tested.
(2) If the clock frequency (f
SCL) is > 100 kHz, use 1-byte write commands for proper operation. All other transactions types are supported at 400 kHz. (Refer to
I2C Interface and
I2C Command Waiting Time).
7.10 Typical Characteristics