SLUSB15J September   2012  – May 2021 BQ2947

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Pin Details
        1. 8.3.1.1 Input Sense Voltage, Vx
        2. 8.3.1.2 Output Drive, OUT
        3. 8.3.1.3 Supply Input, VDD
        4. 8.3.1.4 External Delay Capacitor, CD
    4. 8.4 Device Functional Modes
      1. 8.4.1 NORMAL Mode
      2. 8.4.2 OVERVOLTAGE Mode
      3. 8.4.3 Customer Test Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Configuration for Active High
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

GUID-BFE6B359-36ED-431F-92FE-340F38DCFB02-low.svg Figure 6-1 DSG Package 8-Pin WSONTop View
Table 6-1 Pin Functions
NUMBER NAME TYPE(1) DESCRIPTION
1 VDD P Power supply input
2 V4 IA Sense input for positive voltage of the fourth cell from the bottom of the stack
3 V3 IA Sense input for positive voltage of the third cell from the bottom of the stack
4 V2 IA Sense input for positive voltage of the second cell from the bottom of the stack
5 V1 IA Sense input for positive voltage of the lowest cell in the stack
6 VSS P Electrically connected to IC ground and negative terminal of the lowest cell in the stack
7 CD OA External capacitor connection for delay timer
8 OUT OA Analog Output drive for overvoltage fault signal. Active High or Open Drain Active Low
PowerPAD™ P TI recommends connecting the exposed pad to VSS on the PCB.
(1) IA = Input Analog, OA = Output Analog, P = Power Connection