SLUSCF5C April   2016  – July 2016


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  MP-A5 Coil Specification
      2. 8.3.2  High Voltage Dedicated Charging Port (HVDCP) Negotiation
      3. 8.3.3  Fast Charge Support
      4. 8.3.4  Option Select Pins
      5. 8.3.5  FOD and Parasitic Metal Object Detect (PMOD) Calibration
      6. 8.3.6  FOD Ping Calibration
      7. 8.3.7  Shut Down Through External Thermal Sensor or Trigger
      8. 8.3.8  Fault Handling and Indication
      9. 8.3.9  Power Transfer Start Signal
      10. 8.3.10 Power-On Reset
      11. 8.3.11 External Reset, RESET Pin
      12. 8.3.12 Trickle Charge and CS100
    4. 8.4 Device Functional Modes
      1. 8.4.1 LED Modes
      2. 8.4.2 Power Transfer
      3. 8.4.3 Communication
      4. 8.4.4 Power Trains
      5. 8.4.5 Power Train Voltage Control
      6. 8.4.6 Signal Processing Components
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Capacitor Selection
        2. Current Monitoring Requirements
        3. All Unused Pins
        4. Input Regulators
        5. Input Power Requirements
        6. LED Mode
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

Careful PCB layout practice is critical to proper system operation. Many references are available on proper PCB layout techniques. A few good tips are as follows:

The TX layout requires a 4-layer PCB layout for best ground plane technique. A 2-layer PCB layout can be achieved though not as easily. Ideally, the approach to the layer stack-up is:

  • Layer 1 component placement and as much ground plane as possible
  • Layer 2 clean ground
  • Layer 3 finish routing
  • Layer 4 clean ground

Thus, the circuitry is virtually sandwiched between grounds. This minimizes EMI noise emissions and also provides a noise-free voltage reference plane for device operation.

Keep as much copper as possible. Make sure the bq501210 GND pins and the EPAD GND power pad have a continuous flood connection to the ground plane. The power pad should also be stitched to the ground plane, which also acts as a heat sink for the bq501210. A good GND reference is necessary for proper bq501210 operation, such as analog-digital conversion, clock stability, and best overall EMI performance.

Separate the analog ground plane from the power ground plane and use only one tie point to connect grounds. Having several tie points defeats the purpose of separating the grounds.

The COMM return signal from the resonant tank should be routed as a differential pair. This is intended to reduce stray noise induction. The frequencies of concern warrant low-noise analog signaling techniques, such as differential routing and shielding, but the COMM signal lines do not need to be impedance matched.

The DC-DC buck regulator used from the 19-V input supplies the bq501210 with 3.3-V. Typically, the designer uses a single-chip controller solution with integrated power FET and synchronous rectifier or outboard diode. Pull in the buck inductor and power loop as close as possible to create a tight loop. Likewise, the power-train, full-bridge components should be pulled together as tight as possible. See the bq501210EVM-756 for an example of a good layout technique.

11.2 Layout Example

A DC-DC buck regulator is used to step down the system voltage to the 3.3-V supply to the bq501210. The system voltage is 19-V; with such a step-down ratio, switching duty-cycle is low and the regulator is mostly freewheeling. Therefore, place the freewheeling diode current loop as close to the switching regulator as possible and use wide traces. Place the buck inductor and power loop as close to that as possible to minimize current path.

Place 3.3-V buck regulator input bypass capacitors as close as possible to the buck IC.

bq501210 33V.gif Figure 14. 3.3-V DC-DC Buck Regulator Layout

Make sure the bypass capacitors intended for the bq501210 3.3-V supply are actually bypassing these supply pins (pin 44, V33DIO, pin 45, V33D, and pin 46, V33A) to solid ground plane. This means they need to be placed as close to the device as possible and the traces must be as wide as possible.

bq501210 bq501210IC.gif Figure 15. Bypass Capacitors Layout

Make sure the bq501210 has a continuous flood connection to the ground plane.

bq501210 GND.gif Figure 16. Continuous GND Layout

A buck regulator is used to regulate the supply voltage to the full bridge. The buck power stage IC is controlled by a PWM signal generated by the bq501210 IC, and it is directly powered from the input supply. Because the buck output voltage can operate at a wide voltage range, significant current flow is expected in both the buck power stage input and ground connections. Make sure wide traces and continuous pours are used for input and ground. Place input bypass capacitors, output capacitor and inductor as close as possible to the buck power stage to make the current loop as small as possible.

bq501210 VRAILpower.gif Figure 17. V_RAIL Power Stage Layout

The full-bridge power stage that drives the TX coil is composed of two half-bridge power stages and resonant capacitors. Inputs bypass capacitors should be placed as close as possible to the power stage ICs. The input and ground pours and traces should be made as wide as possible for better current flow. The trace to the coil and resonant capacitors should also be made as wide as possible.

bq501210 GndRes.gif Figure 18. Ground Layout

To ensure proper operation, grounds conducting a large amount of current and switching noise must be isolated from low current, quiet grounds. Separate the ground pours for the power stages and the bq501210 IC. Connect all grounds to a single point at the main ground terminal.

bq501210 GNDLayer.gif Figure 19. Ground Layout

Proper current sensing layout technique is very important, as it directly affects the FOD and PMOD performance. When sampling the very-low voltages generated across a current sense resistor, be sure to use the so called 4-wire or Kelvin-connection technique. This is important to avoid introducing false voltage drops from adjacent pads and copper power routes. It is a common power-supply layout technique. Some high-accuracy sense resistors have dedicated sense pins.

bq501210 ISense.gif Figure 20. Current Sensing Layout

The COMM+/COMM– sense lines should be run as a balanced or differential pair. For communication, the WPC packet information runs at 2 kHz, which is essentially audio frequency content, and this balancing reduces noise pickup from the surrounding switching power electronics. The designer does not need to tune or impedance-match these lines as would be the case in RF signaling. It is important to keep this lines isolated from any fast switching signal such as PWM, to prevent noise from being injected into the line.

The V_RAIL+/VRAIL– sense lines should also run as differential pair. Figure 21 shows a layout example for a differential pair layout.

bq501210 Balance.gif Figure 21. Balanced Differential Signal Layout

A bypass capacitor needs to be connected between the point where the 3.3-V bias supply is connected to the COMM+ resistor divider and the divider/COMM– ground connection.

bq501210 COMM.gif Figure 22. Bypass Capacitors Layout for COMM+ Resistor Divider 3.3-V Bias