SLUSCF5C April 2016 – July 2016
Careful PCB layout practice is critical to proper system operation. Many references are available on proper PCB layout techniques. A few good tips are as follows:
The TX layout requires a 4-layer PCB layout for best ground plane technique. A 2-layer PCB layout can be achieved though not as easily. Ideally, the approach to the layer stack-up is:
Thus, the circuitry is virtually sandwiched between grounds. This minimizes EMI noise emissions and also provides a noise-free voltage reference plane for device operation.
Keep as much copper as possible. Make sure the bq501210 GND pins and the EPAD GND power pad have a continuous flood connection to the ground plane. The power pad should also be stitched to the ground plane, which also acts as a heat sink for the bq501210. A good GND reference is necessary for proper bq501210 operation, such as analog-digital conversion, clock stability, and best overall EMI performance.
Separate the analog ground plane from the power ground plane and use only one tie point to connect grounds. Having several tie points defeats the purpose of separating the grounds.
The COMM return signal from the resonant tank should be routed as a differential pair. This is intended to reduce stray noise induction. The frequencies of concern warrant low-noise analog signaling techniques, such as differential routing and shielding, but the COMM signal lines do not need to be impedance matched.
The DC-DC buck regulator used from the 19-V input supplies the bq501210 with 3.3-V. Typically, the designer uses a single-chip controller solution with integrated power FET and synchronous rectifier or outboard diode. Pull in the buck inductor and power loop as close as possible to create a tight loop. Likewise, the power-train, full-bridge components should be pulled together as tight as possible. See the bq501210EVM-756 for an example of a good layout technique.
A DC-DC buck regulator is used to step down the system voltage to the 3.3-V supply to the bq501210. The system voltage is 19-V; with such a step-down ratio, switching duty-cycle is low and the regulator is mostly freewheeling. Therefore, place the freewheeling diode current loop as close to the switching regulator as possible and use wide traces. Place the buck inductor and power loop as close to that as possible to minimize current path.
Place 3.3-V buck regulator input bypass capacitors as close as possible to the buck IC.
Make sure the bypass capacitors intended for the bq501210 3.3-V supply are actually bypassing these supply pins (pin 44, V33DIO, pin 45, V33D, and pin 46, V33A) to solid ground plane. This means they need to be placed as close to the device as possible and the traces must be as wide as possible.
Make sure the bq501210 has a continuous flood connection to the ground plane.
A buck regulator is used to regulate the supply voltage to the full bridge. The buck power stage IC is controlled by a PWM signal generated by the bq501210 IC, and it is directly powered from the input supply. Because the buck output voltage can operate at a wide voltage range, significant current flow is expected in both the buck power stage input and ground connections. Make sure wide traces and continuous pours are used for input and ground. Place input bypass capacitors, output capacitor and inductor as close as possible to the buck power stage to make the current loop as small as possible.
The full-bridge power stage that drives the TX coil is composed of two half-bridge power stages and resonant capacitors. Inputs bypass capacitors should be placed as close as possible to the power stage ICs. The input and ground pours and traces should be made as wide as possible for better current flow. The trace to the coil and resonant capacitors should also be made as wide as possible.
To ensure proper operation, grounds conducting a large amount of current and switching noise must be isolated from low current, quiet grounds. Separate the ground pours for the power stages and the bq501210 IC. Connect all grounds to a single point at the main ground terminal.
Proper current sensing layout technique is very important, as it directly affects the FOD and PMOD performance. When sampling the very-low voltages generated across a current sense resistor, be sure to use the so called 4-wire or Kelvin-connection technique. This is important to avoid introducing false voltage drops from adjacent pads and copper power routes. It is a common power-supply layout technique. Some high-accuracy sense resistors have dedicated sense pins.
The COMM+/COMM– sense lines should be run as a balanced or differential pair. For communication, the WPC packet information runs at 2 kHz, which is essentially audio frequency content, and this balancing reduces noise pickup from the surrounding switching power electronics. The designer does not need to tune or impedance-match these lines as would be the case in RF signaling. It is important to keep this lines isolated from any fast switching signal such as PWM, to prevent noise from being injected into the line.
The V_RAIL+/VRAIL– sense lines should also run as differential pair. Figure 21 shows a layout example for a differential pair layout.
A bypass capacitor needs to be connected between the point where the 3.3-V bias supply is connected to the COMM+ resistor divider and the divider/COMM– ground connection.