SLUSFC9 December   2023 BQ76972

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information BQ76952
    5. 6.5  Supply Current
    6. 6.6  Digital I/O
    7. 6.7  LD Pin
    8. 6.8  Precharge (PCHG) and Predischarge (PDSG) FET Drive
    9. 6.9  FUSE Pin Functionality
    10. 6.10 REG18 LDO
    11. 6.11 REG0 Pre-regulator
    12. 6.12 REG1 LDO
    13. 6.13 REG2 LDO
    14. 6.14 Voltage References
    15. 6.15 Coulomb Counter
    16. 6.16 Coulomb Counter Digital Filter (CC1)
    17. 6.17 Current Measurement Digital Filter (CC2)
    18. 6.18 Current Wake Detector
    19. 6.19 Analog-to-Digital Converter
    20. 6.20 Cell Voltage Measurement Accuracy
    21. 6.21 Cell Balancing
    22. 6.22 Cell Open Wire Detector
    23. 6.23 Internal Temperature Sensor
    24. 6.24 Thermistor Measurement
    25. 6.25 Internal Oscillators
    26. 6.26 High-side NFET Drivers
    27. 6.27 Comparator-Based Protection Subsystem
    28. 6.28 Timing Requirements - I2C Interface, 100kHz Mode
    29. 6.29 Timing Requirements - I2C Interface, 400kHz Mode
    30. 6.30 Timing Requirements - HDQ Interface
    31. 6.31 Timing Requirements - SPI Interface
    32. 6.32 Interface Timing Diagrams
    33. 6.33 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  BQ76972 Device Versions
    4. 7.4  Diagnostics
    5. 7.5  Device Configuration
      1. 7.5.1 Commands and Subcommands
      2. 7.5.2 Configuration Using OTP or Registers
      3. 7.5.3 Device Security
      4. 7.5.4 Scratchpad Memory
    6. 7.6  Measurement Subsystem
      1. 7.6.1  Voltage Measurement
        1. 7.6.1.1 Voltage Measurement Schedule
        2. 7.6.1.2 Usage of VC Pins for Cells Versus Interconnect
        3. 7.6.1.3 Cell 1 Voltage Validation During SLEEP Mode
      2. 7.6.2  General Purpose ADCIN Functionality
      3. 7.6.3  Coulomb Counter and Digital Filters
      4. 7.6.4  Synchronized Voltage and Current Measurement
      5. 7.6.5  Internal Temperature Measurement
      6. 7.6.6  Thermistor Temperature Measurement
      7. 7.6.7  Factory Trim of Voltage ADC
      8. 7.6.8  Cell Voltage Measurement Accuracy
        1. 7.6.8.1 Fixed Offset Adjustment
        2. 7.6.8.2 Cell Offset Calibration
      9. 7.6.9  Voltage Calibration (ADC Measurements)
      10. 7.6.10 Voltage Calibration (COV and CUV Protections)
      11. 7.6.11 Current Calibration
      12. 7.6.12 Temperature Calibration
    7. 7.7  Primary and Secondary Protection Subsystems
      1. 7.7.1 Protections Overview
      2. 7.7.2 Primary Protections
      3. 7.7.3 Secondary Protections
      4. 7.7.4 High-Side NFET Drivers
      5. 7.7.5 Protection FETs Configuration and Control
        1. 7.7.5.1 FET Configuration
        2. 7.7.5.2 PRECHARGE and PREDISCHARGE Modes
      6. 7.7.6 Load Detect Functionality
    8. 7.8  Device Hardware Features
      1. 7.8.1  Voltage References
      2. 7.8.2  ADC Multiplexer
      3. 7.8.3  LDOs
        1. 7.8.3.1 Preregulator Control
        2. 7.8.3.2 REG1 and REG2 LDO Controls
      4. 7.8.4  Standalone Versus Host Interface
      5. 7.8.5  Multifunction Pin Controls
      6. 7.8.6  RST_SHUT Pin Operation
      7. 7.8.7  CFETOFF, DFETOFF, and BOTHOFF Pin Functionality
      8. 7.8.8  ALERT Pin Operation
      9. 7.8.9  DDSG and DCHG Pin Operation
      10. 7.8.10 Fuse Drive
      11. 7.8.11 Cell Open Wire
      12. 7.8.12 Low Frequency Oscillator
      13. 7.8.13 High Frequency Oscillator
    9. 7.9  Device Functional Modes
      1. 7.9.1 Overview
      2. 7.9.2 NORMAL Mode
      3. 7.9.3 SLEEP Mode
      4. 7.9.4 DEEPSLEEP Mode
      5. 7.9.5 SHUTDOWN Mode
      6. 7.9.6 CONFIG_UPDATE Mode
    10. 7.10 Serial Communications Interface
      1. 7.10.1 Serial Communications Overview
      2. 7.10.2 I2C Communications
      3. 7.10.3 SPI Communications
        1. 7.10.3.1 SPI Protocol
      4. 7.10.4 HDQ Communications
    11. 7.11 Cell Balancing
      1. 7.11.1 Cell Balancing Overview
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design Requirements (Example)
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Performance Plot
      4. 8.2.4 Calibration Process
    3. 8.3 Random Cell Connection Support
    4. 8.4 Startup Timing
    5. 8.5 FET Driver Turn-Off
    6. 8.6 Unused Pins
    7. 8.7 Power Supply Requirements
    8. 8.8 Layout
      1. 8.8.1 Layout Guidelines
      2. 8.8.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
DESCRIPTION PINS MIN MAX UNIT
Supply voltage range BAT VSS–0.3 VSS+85 V
Input voltage range, VIN PACK, LD VSS–0.3 VSS+85 V
Input voltage range, VIN PCHG, PDSG the maximum of VBAT–10 or VLD–10  VSS+85 V
Input voltage range, VIN REGIN the maximum of VSS–0.3 or VBREG–5.5 the minimum of VSS+6 or VBAT+0.3 or VBREG+0.3 V
Input voltage range, VIN FUSE(2) VSS–0.3 the minimum of VSS+20 or VBAT+0.3 V
Input voltage range, VIN BREG the maximum of VSS–0.3 or VREGIN–0.3 VREGIN+5.5 V
Input voltage range, VIN REG1, REG2 VSS–0.3 minimum of VSS+6 or VREGIN+0.3 V
Input voltage range, VIN ALERT, SCL, SDA, HDQ, CFETOFF, DFETOFF, DCHG, DDSG, RST_SHUT (3) VSS–0.3 VSS+6 V
Input voltage range, VIN TS1, TS2, TS3, ALERT, CFETOFF, DFETOFF, HDQ, DCHG, DDSG (when used as thermistor or general purpose ADC input) VSS–0.3 VREG18 + 0.3 V
Input voltage range, VIN SRP, SRN VSS–0.3 VREG18 + 0.3 V
Input voltage range, VIN VC16 maximum of VSS–0.3 and VC15–0.3 VSS+85 V
Input voltage range, VIN VC15 maximum of VSS–0.3 and VC14–0.3 VSS+85 V
Input voltage range, VIN VC14 maximum of VSS–0.3 and VC13–0.3 VSS+85 V
Input voltage range, VIN VC13 maximum of VSS–0.3 and VC12–0.3 VSS+85 V
Input voltage range, VIN VC12 maximum of VSS–0.3 and VC11–0.3 VSS+85 V
Input voltage range, VIN VC11 maximum of VSS–0.3 and VC10–0.3 VSS+85 V
Input voltage range, VIN VC10 maximum of VSS–0.3 and VC9–0.3 VSS+85 V
Input voltage range, VIN VC9 maximum of VSS–0.3 and VC8–0.3 VSS+85 V
Input voltage range, VIN VC8 maximum of VSS–0.3 and VC7–0.3 VSS+85 V
Input voltage range, VIN VC7 maximum of VSS–0.3 and VC6–0.3 VSS+85 V
Input voltage range, VIN VC6 maximum of VSS–0.3 and VC5–0.3 VSS+85 V
Input voltage range, VIN VC5 maximum of VSS–0.3 and VC4–0.3 VSS+85 V
Input voltage range, VIN VC4 maximum of VSS–0.3 and VC3–0.3 VSS+85 V
Input voltage range, VIN VC3 maximum of VSS–0.3 and VC2–0.3 VSS+85 V
Input voltage range, VIN VC2 maximum of VSS–0.3 and VC1–0.3 VSS+85 V
Input voltage range, VIN VC1 maximum of VSS–0.3 and VC0–0.3 VSS+85 V
Input voltage range, VIN VC0 VSS–0.3 VSS+6 V
Output voltage range, VO CP1 VBAT–0.3 the minimum of VSS+85 or VBAT+15 V
Output voltage range, VO CHG VSS–0.3 VSS+85 V
Output voltage range, VO DSG VSS–0.3 VSS+85 V
Output voltage range, VO REG1, REG2, TS2 (for wakeup function), ALERT, CFETOFF, DFETOFF, HDQ, DCHG, DDSG, when configured to drive a digital output VSS–0.3 VSS+6 V
Output voltage range, VO REG18 VSS–0.3 VSS+2 V
Maximum cell balancing current through a single cell VC0 – VC16 100 mA
Maximum VSS current, ISS 75 mA
Functional temperature, TFUNC –40 85 °C
Junction temperature, TJ –55 150 °C
Storage temperature, TSTG –55 150 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The current allowed to flow into the FUSE pin must be limited (such as by using external series resistance) to 2 mA or less.
(3) When the ALERT, HDQ, CFETOFF, DFETOFF, DCHG, or DDSG pins are selected for thermistor input or general purpose ADC–input, their voltage is limited to VREG18 + 0.3 V. These pins can accept up to 6 V when configured for other uses, such as a digital input.