11.1 Layout Guidelines

• The layout for the high-current path begins at the PACK+ pin of the battery pack. As charge current travels through the pack, it finds its way through protection FETs, a chemical fuse, the lithium-ion cells and cell connections, and the sense resistor, and then returns to the PACK– pin. In addition, some components are placed across the PACK+ and PACK– pins to reduce effects from electrostatic discharge.
• The N-channel charge and discharge FETs must be selected for a given application. Most portable battery applications are a good option for the CSD16412Q5A. These FETs are rated at 14-A, 25-V device with Rds(on) of 11 mΩ when the gate drive voltage is 10 V. The gates of all protection FETs are pulled to the source with a high-value resistor between the gate and source to ensure they are turned off if the gate drive is open. The capacitors (both 0.1 µF values) placed across the FETs are to help protect the FETs during an ESD event. The use of two devices ensures normal operation if one of them becomes shorted. For effective ESD protection, the copper trace inductance of the capacitor leads must be designed to be as short and wide as possible. Ensure that the voltage rating of both these capacitors are adequate to hold off the applied voltage if one of the capacitors becomes shorted.
• The quality of the Kelvin connections at the sense resistor is critical. The sense resistor must have a temperature coefficient no greater than 50 ppm in order to minimize current measurement drift with temperature. Choose the value of the sense resistor to correspond to the available overcurrent and short-circuit ranges of the bq78z100. Select the smallest value possible in order to minimize the negative voltage generated on the bq78z100 VSS node(s) during a short circuit. This pin has an absolute minimum of –0.3 V. Parallel resistors can be used as long as good Kelvin sensing is ensured. The device is designed to support a 1-mΩ to 3-mΩ sense resistor.
• A pair of series 0.1-μF ceramic capacitors is placed across the PACK+ and PACK– pins to help in the mitigation of external electrostatic discharges. The two devices in series ensure continued operation of the pack if one of the capacitors becomes shorted. Optionally, a transorb such as the SMBJ2A can be placed across the pins to further improve ESD immunity.
• In reference to the gas gauge circuit the following features require attention for component placement and layout; Differential Low-Pass Filter, I²C communication and PBI (Power Backup Input).
• The bq78z100 uses an integrating delta-sigma ADC for current measurements. Add a 100-Ω resistor from the sense resistor to the SRP and SRN inputs of the device. Place a 0.1-μF filter capacitor across the SRP and SRN inputs. Optional 0.1-μF filter capacitors can be added for additional noise filtering for each sense input pin to ground, if required for your circuit. Place all filter components as close as possible to the device. Route the traces from the sense resistor in parallel to the filter circuit. Adding a ground plane around the filter network can add additional noise immunity.
Figure 24. bq78z100 Differential Filter

• The bq78z100 has an internal LDO that is internally compensated and does not require an external decoupling capacitor. The PBI pin is used as a power supply backup input pin, providing power during brief transient power outages. A standard 2.2-μF ceramic capacitor is connected from the PBI pin to ground, as shown in application example.
• The I²C clock and data pins have integrated high-voltage ESD protection circuits; however, adding a Zener diode and series resistor provides more robust ESD performance. The I²C clock and data lines have an internal pull-down. When the gas gauge senses that both lines are low (such as during removal of the pack), the device performs auto-offset calibration and then goes into SLEEP mode to conserve power.

11.2 Layout Example

Figure 25. bq78z100 Board Layout