The following design guidelines must be followed when laying out the CC3220x device:
- Route all of the input decoupling capacitors (C11, C13, and C18) on L2 using thick traces, to isolate the RF ground from the noisy supply ground. This step is also required to meet the IEEE spectral mask specifications.
- Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power amplifier supply lines (pins 33, 40, 41, and 42), and all input supply pins (pins 37, 39, and 44).
- Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).
- Place all decoupling capacitors as close to the respective pins as possible.
- Power budget: The CC3220x device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, and 700 mA for 1.85 V, for 24 ms during the calibration cycle.
- Ensure the power supply is designed to source this current without any issues. The complete calibration (TX and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.
- The CC3220x device contains many high-current input pins. Ensure the trace feeding these pins is capable of handling the following currents:
- VIN_DCDC_PA input (pin 39) maximum is 1 A
- VIN_DCDC_ANA input (pin 37) maximum is 600 mA
- VIN_DCDC_DIG input (pin 44) maximum is 500 mA
- DCDC_PA_SW_P (pin 40) and DCDC_PA_SW_N (pin 41) switching nodes maximum is 1 A
- DCDC_PA_OUT output node (pin 42) maximum 1 A
- DCDC_ANA_SW switching node (pin 38) maximum is 600 mA
- DCDC_DIG_SW switching node (pin 43) maximum is 500 mA
- VDD_PA_IN supply (pin 33) maximum is 500 mA
Figure 10-3 shows the ground routing for the input decoupling capacitors.
Figure 10-3 Ground Routing for the Input Decoupling Capacitors
The ground return for the input capacitors are routed on L2 to reduce the EMI and improve the spectral mask. This routing must be strictly followed because it is critical for the overall performance of the device.