7 Parameter Measurement Information

Figure 7-1 Typical Bias Voltages

Note:

The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = V_SS
and 1 = V_DD. The analog signal (through the TG) may swing from V_EE to V_DD.

Figure 7-2 Waveforms, Channel Being Turned ON (R_L = 1 kΩ)

Figure 7-3 Waveforms, Channel Being Turned OFF (R_L = 1 kΩ)

Figure 7-4 OFF Channel Leakage Current – Any Channel OFF

Figure 7-5 On Channel Leakage Current – Any Channel On

Figure 7-6 OFF Channel Leakage Current – All Channels OFF

Figure 7-7 Propagation Delay – Address Input to Signal Output

Figure 7-8 Propagation Delay – Inhibit Input to Signal Output

Figure 7-9 Input Voltage Test Circuits (Noise Immunity)

Figure 7-10 Quiescent Device Current

Figure 7-11 Channel ON Resistance Measurement Circuit

Figure 7-12 Input Current

Figure 7-13 Feed-Through (All Types)

Figure 7-14 Crosstalk Between Any Two Channels (All Types)

Figure 7-15 Crosstalk Between Duals or Triplets (CD4053B-Q1)

Figure 7-16 24-to-1 MUX Addressing