SCHS354D August   1998  – March 2025 CD4051B-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - CD4051B-Q1
    6. 5.6 AC Performance Characteristics - CD4051B-Q1
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

CD4051B-Q1 CD4051B-Q1D or PW Package,(Top View)Figure 4-1 CD4051B-Q1D or PW Package,(Top View)
Table 4-1 Pin Functions CD4051B-Q1
PINTYPE(1)DESCRIPTION
NO.NAME
1

CH 4 IN/OUT

I/O

Channel 4 in/out

2

CH 6 IN/OUT

I/O

Channel 6 in/out

3

COM OUT/IN

I/O

Common out/in

4

CH 7 IN/OUT

I/O

Channel 7 in/out

5

CH 5 IN/OUT

I/O

Channel 5 in/out

6INHIDisables all channels. See Table 7-1.
7VEE—Negative power input
8VSS—Ground
9CIChannel select C. See Table 7-1.
10BIChannel select B. See Table 7-1.
11AIChannel select A. See Table 7-1.
12

CH 3 IN/OUT

I/O

Channel 3 in/out

13

CH 0 IN/OUT

I/O

Channel 0 in/out

14

CH 1 IN/OUT

I/O

Channel 1 in/out

15

CH 2 IN/OUT

I/O

Channel 2 in/out

16VDD—Positive power input
(1) I = input, O = output