SCHS047K August   1998  – March 2023 CD4051B , CD4052B , CD4053B

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics – TSSOP Package 
    6. 6.6 AC Performance Characteristics – TSSOP Package
    7. 6.7 Electrical Characteristics – CDIP, PDIP, SOIC and SOP Packages
    8. 6.8 AC Performance Characteristics – CDIP, PDIP, SOIC and SOP Packages
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Wide range of digital and analog signal levels:
    • Digital: 3 V to 20 V
    • Analog: ≤ 20 VP-P
  • Low ON resistance, 125 Ω (typical) over 15 VP-P signal input range for VDD – VEE = 18 V
  • High OFF resistance, channel leakage of
    ±100 pA (typical) at VDD – VEE = 18 V
  • Logic-level conversion for digital addressing signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) to switch analog signals to 20 VP-P (VDD – VEE = 20 V) matched switch characteristics, rON = 5 Ω (typical) for VDD – VEE = 15 V very low quiescent power dissipation under all digital-control input and supply conditions, 0.2 µW (typical) at
    VDD – VSS = VDD – VEE = 10 V
  • Binary address decoding on chip
  • 5 V, 10 V, and 15 V parametric ratings
  • 100% tested for quiescent current at 20 V
  • Maximum input current of 1 µA at 18 V over full package temperature range, 100 nA at 18 V and 25°C
  • Break-before-make switching eliminates channel overlap