SCHS047I August   1998  – September 2017 CD4051B , CD4052B , CD4053B

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 AC Performance Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • NS|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Wide Range of Digital and Analog Signal Levels
    • Digital: 3 V to 20 V
    • Analog: ≤20 VP-P
  • Low ON Resistance,125 Ω (Typical) Over 15 VP-P Signal Input Range for VDD – VEE = 18 V
  • High OFF Resistance, Channel Leakage of ±100 pA (Typical) at VDD – VEE = 18 V
  • Logic-Level Conversion for Digital Addressing Signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) to Switch Analog Signals to 20 VP-P (VDD – VEE = 20 V) Matched Switch Characteristics, rON = 5 Ω (Typical) for VDD – VEE = 15 V Very Low Quiescent Power Dissipation Under All Digital-Control Input and Supply Conditions, 0.2 µW (Typical) at VDD – VSS = VDD – VEE = 10 V
  • Binary Address Decoding on Chip
  • 5 V, 10 V, and 15 V Parametric Ratings
  • 100% Tested for Quiescent Current at 20 V
  • Maximum Input Current of 1 µA at 18 V Over Full Package Temperature Range, 100 nA at 18 V and 25°C
  • Break-Before-Make Switching Eliminates Channel Overlap

Applications

  • Analog and Digital Multiplexing and Demultiplexing
  • A/D and D/A Conversion
  • Signal Gating
  • Factory Automation
  • Televisions
  • Appliances
  • Consumer Audio
  • Programmable Logic Circuits
  • Sensors

Description

The CD405xB analog multiplexers and demuliplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full VDD – VSS and VDD – VEE supply-voltage ranges, independent of the logic state of the control signals.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
CD405xB CDIP (16) 19.50 mm × 6.92 mm
PDIP (16) 19.30 mm × 6.35 mm
SOIC (16) 9.90 mm × 3.91 mm
SOP (16) 10.30 mm × 5.30 mm
TSSOP (16) 5.00 mm × 4.40 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Functional Diagrams of CD405xB

CD4051B CD4052B CD4053B cd405xb_fbd.gif

Revision History

Changes from H Revision (April 2015) to I Revision

  • Added: ON Channel Leakage Current to the Electrical Characteristics table Go
  • Added Note 3 to the Electrical Characteristics tableGo
  • Added Figure 13Go

Changes from G Revision (October 2003) to H Revision

  • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go
  • Added Device Information table.Go