20-V, 8:1, 1-channel analog multiplexer with logic-level conversion
Product details
Parameters
Package | Pins | Size
Features
- Wide Range of Digital and Analog Signal Levels
- Digital: 3 V to 20 V
- Analog: ≤ 20 VP-P
- Low ON Resistance, 125 Ω (Typical) Over 15 VP-P Signal Input Range for VDD – VEE = 18 V
- High OFF Resistance, Channel Leakage of
±100 pA (Typical) at VDD – VEE = 18 V - Logic-Level Conversion for Digital Addressing Signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) to Switch Analog Signals to 20 VP-P (VDD – VEE = 20 V) Matched Switch Characteristics, rON = 5 Ω (Typical) for VDD – VEE = 15 V Very Low Quiescent Power Dissipation Under All Digital-Control Input and Supply Conditions, 0.2 µW (Typical) at
VDD – VSS = VDD – VEE = 10 V - Binary Address Decoding on Chip
- 5 V, 10 V, and 15 V Parametric Ratings
- 100% Tested for Quiescent Current at 20 V
- Maximum Input Current of 1 µA at 18 V Over Full Package Temperature Range, 100 nA at 18 V and 25°C
- Break-Before-Make Switching Eliminates Channel Overlap
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Description
The CD405xB analog multiplexers and demultiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full VDD – VSS and VDD – VEE supply-voltage ranges, independent of the logic state of the control signals.
Technical documentation
= Top documentation for this product selected by TI
| Type | Title | Date | |
|---|---|---|---|
| * | Datasheet | CD405xB CMOS Single 8-Channel Analog Multiplexer/Demultiplexer with Logic-Level Conversion datasheet (Rev. I) | Aug. 31, 2017 |
| Application notes | Selecting the Right Texas Instruments Signal Switch (Rev. B) | Apr. 02, 2020 | |
| Application notes | Multiplexers and Signal Switches Glossary | Mar. 06, 2020 | |
| Technical articles | Roll with the design punches and overcome power-sequencing challenges | Jul. 29, 2019 | |
| Selection guides | Logic Guide (Rev. AB) | Jun. 12, 2017 | |
| Application notes | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | Dec. 02, 2015 | |
| User guides | LOGIC Pocket Data Book (Rev. B) | Jan. 16, 2007 | |
| Application notes | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | Jul. 08, 2004 | |
| User guides | Signal Switch Data Book (Rev. A) | Nov. 14, 2003 | |
| More literature | Logic Cross-Reference (Rev. A) | Oct. 07, 2003 | |
| Application notes | Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics | Dec. 03, 2001 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
LEADED-ADAPTER1
Description
The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages. The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.
Features
- Quick testing of TI's leaded surface mount packages
- Allows leaded suface mount packages to be plugged into 100mil spaced bread board
- Supports TI's 8 most popular leaded packages with a single panel
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 16 | View options |
| SO (NS) | 16 | View options |
| SOIC (D) | 16 | View options |
| TSSOP (PW) | 16 | View options |
Ordering & quality
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