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CD4051B

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20-V, 8:1, 1-channel analog multiplexer with logic-level conversion

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Data sheet

CD4051B

ACTIVE
Data sheet Order now

Product details

Configuration 8:1 Number of channels (#) 1 Power supply voltage - single (V) 3.3, 5, 12, 16, 20 Protocols Analog Ron (Typ) (Ohms) 125 CON (Typ) (pF) 30 ON-state leakage current (Max) (µA) 0.3 Bandwidth (MHz) 20 Operating temperature range (C) -55 to 125 Features Break-before-make Input/output continuous current (Max) (mA) 10 Rating Catalog Supply current (Typ) (uA) 0.04
Configuration 8:1 Number of channels (#) 1 Power supply voltage - single (V) 3.3, 5, 12, 16, 20 Protocols Analog Ron (Typ) (Ohms) 125 CON (Typ) (pF) 30 ON-state leakage current (Max) (µA) 0.3 Bandwidth (MHz) 20 Operating temperature range (C) -55 to 125 Features Break-before-make Input/output continuous current (Max) (mA) 10 Rating Catalog Supply current (Typ) (uA) 0.04
PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 TSSOP (PW) 16 22 mm² 4.4 x 5 TSSOP (PW) 16 22 mm² 5 x 4.4
  • Wide Range of Digital and Analog Signal Levels
    • Digital: 3 V to 20 V
    • Analog: ≤ 20 VP-P
  • Low ON Resistance, 125 Ω (Typical) Over 15 VP-P Signal Input Range for VDD – VEE = 18 V
  • High OFF Resistance, Channel Leakage of
    ±100 pA (Typical) at VDD – VEE = 18 V
  • Logic-Level Conversion for Digital Addressing Signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) to Switch Analog Signals to 20 VP-P (VDD – VEE = 20 V) Matched Switch Characteristics, rON = 5 Ω (Typical) for VDD – VEE = 15 V Very Low Quiescent Power Dissipation Under All Digital-Control Input and Supply Conditions, 0.2 µW (Typical) at
    VDD – VSS = VDD – VEE = 10 V
  • Binary Address Decoding on Chip
  • 5 V, 10 V, and 15 V Parametric Ratings
  • 100% Tested for Quiescent Current at 20 V
  • Maximum Input Current of 1 µA at 18 V Over Full Package Temperature Range, 100 nA at 18 V and 25°C
  • Break-Before-Make Switching Eliminates Channel Overlap
  • Wide Range of Digital and Analog Signal Levels
    • Digital: 3 V to 20 V
    • Analog: ≤ 20 VP-P
  • Low ON Resistance, 125 Ω (Typical) Over 15 VP-P Signal Input Range for VDD – VEE = 18 V
  • High OFF Resistance, Channel Leakage of
    ±100 pA (Typical) at VDD – VEE = 18 V
  • Logic-Level Conversion for Digital Addressing Signals of 3 V to 20 V (VDD – VSS = 3 V to 20 V) to Switch Analog Signals to 20 VP-P (VDD – VEE = 20 V) Matched Switch Characteristics, rON = 5 Ω (Typical) for VDD – VEE = 15 V Very Low Quiescent Power Dissipation Under All Digital-Control Input and Supply Conditions, 0.2 µW (Typical) at
    VDD – VSS = VDD – VEE = 10 V
  • Binary Address Decoding on Chip
  • 5 V, 10 V, and 15 V Parametric Ratings
  • 100% Tested for Quiescent Current at 20 V
  • Maximum Input Current of 1 µA at 18 V Over Full Package Temperature Range, 100 nA at 18 V and 25°C
  • Break-Before-Make Switching Eliminates Channel Overlap

The CD405xB analog multiplexers and demultiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full VDD – VSS and VDD – VEE supply-voltage ranges, independent of the logic state of the control signals.

The CD405xB analog multiplexers and demultiplexers are digitally-controlled analog switches having low ON impedance and very low OFF leakage current. These multiplexer circuits dissipate extremely low quiescent power over the full VDD – VSS and VDD – VEE supply-voltage ranges, independent of the logic state of the control signals.
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Technical documentation

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Type Title Date
* Data sheet CD405xB CMOS Single 8-Channel Analog Multiplexer/Demultiplexer with Logic-Level Conversion datasheet (Rev. I) 31 Aug 2017
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. D) 09 Dec 2021
Application note Multiplexers and Signal Switches Glossary (Rev. B) 01 Dec 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics 03 Dec 2001

Design & development

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Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

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PDIP (N) 16 View options
SO (NS) 16 View options
SOIC (D) 16 View options
TSSOP (PW) 16 View options

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