SCHS188E November   1998  – October 2022 CD54HC534 , CD54HC564 , CD54HCT534 , CD54HCT564 , CD74HC534 , CD74HC564 , CD74HCT534 , CD74HCT564

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings (1)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Prerequisite for Switching Characteristics
    6. 5.6 Switching Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • N|20
  • DW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

CL = 50 pF, Input tr, tf = 6 ns
PARAMETER VCC (V) 25℃ –40℃ to 85℃ –55℃ to 125℃ UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
tPLH, tPHL Propagation delay clock to output 2 165 205 250 ns
4.5 13(3) 33 41 50
6 28 35 43
tPL, tPHZ Output disable to Q (534) 2 150 190 225 ns
4.5 12(3) 30 38 45
6 26 33 38
tPLZ, tPHZ Output disable to Q (564) 2 135 170 205 ns
4.5 12(3) 27 34 41
6 23 29 35
tPZL, tPZH Output enable to Q 2 150 190 225 ns
4.5 12(3) 30 38 45
6 26 33 38
fMAX Maximum clock frequency 5 60(4) MHz
tTHL, tTLH Output transition time 2 60 75 90 ns
4.5 12 15 18
6 10 13 15
CI Input capacitance 10 10 10 10 pF
CO Three-state output capacitance 20 20 20 20 pF
CPD Power dissipation capacitance(1)(2) 5 32 pF
HCT TYPES
tPHL, tPLH Propagation delay clock to output 4.5 14(3) 35 44 53 ns
tPLZ, tPHZ Output disable to Q 4.5 12(3) 30 38 45 ns
tPHL, tPZH Output enable to Q 4.5 14(3) 35 44 53 ns
fMAX Maximum clock frequency 5 50(4) MHz
tTLH, tTHL Output transition time 4.5 12 15 18 ns
CI Input capacitance 10 10 10 10 pF
CO Three-state output capacitance 20 20 20 20 pF
CPD Power dissipation capacitance(1)(2) 5 36 pF
(1) CPD is used to determine the dynamic power consumption, per package.
(2) PD = CPD VCC2 fi + Σ CL VCC2 fO where fi = input frequency, fO = output frequency, CL = output load capacitance, VCC = supply voltage.
(3) CL = 15 pF and VCC = 5 V.
(4) CL = 15 pF.