High Speed CMOS Logic Octal Positive-Edge-Triggered D-Type Inverting Flip-Flops with 3-State Outputs


Product details


Technology Family HCT Input type TTL-Compatible CMOS Output type 3-State VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 8 Clock Frequency (Max) (MHz) 25 ICC (uA) 80 IOL (Max) (mA) 6 IOH (Max) (mA) -6 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode Rating Catalog open-in-new Find other D-type flip-flop

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 open-in-new Find other D-type flip-flop


  • Buffered Inputs
  • Common Three-State Output-Enable Control
  • Three-State Outputs
  • Bus Line Driving Capability
  • Typical Propagation Delay = 13ns at VCC = 5V, CL = 15pF, TA = 25°C (Clock to Output)
  • Fanout (Over Temperature Range)
    • Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
    • Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . -55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
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The ’HC534, ’HCT534, ’HC564, and ’HCT564 are high speed Octal D-Type Flip-Flops manufactured with silicon gate CMOS technology. They possess the low power consumption of stan-dard CMOS integrated circuits, as well as the ability to drive 15 LSTTL loads. Due to the large output drive capability and the three-state feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. The two types are functionally identical and differ only in their pinout arrangements.

The ’HC534, ’HCT534, ’HC564, and ’HCT564 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are inverted and trans-ferred to the Q outputs on the positive going transition of the CLOCK input. When a high logic level is applied to the OUT-PUT ENABLE input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.

The HCT logic family is speed, function, and pin compatible with the standard LS logic family.

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Technical documentation

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Type Title Date
* Datasheet CD54/74HC534, CD54/74HCT534, CD54/74HC564, CD54/74HCT564 datasheet (Rev. C) Apr. 22, 2004
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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Hardware development

document-generic User guide
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

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PDIP (N) 20 View options

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