SCLS455E February   2001  – June 2022 CD54HCT573 , CD74HCT573

PRODUCTION DATA  

  1. 1 Features
  2. 2 Description
  3. 3 Revision History
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions (1)
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Timing Requirements
    6. 5.6 Switching Characteristics
    7. 5.7 Operating Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. 8 Power Supply Recommendations
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|20
  • N|20
  • DW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Description

The ’HCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
CD74HCT573M SOIC (20) 12.80 mm × 7.50 mm
CD74HCT573DBR SSOP (20) 7.20 mm × 5.30 mm
CD74HCT573E PDIP (20) 25.40 mm × 6.35 mm
CD54HCT573F CDIP (20) 26.92 mm × 6.92 mm
(1) For all available packages, see the orderable addendum at the end of the data sheet.
GUID-20210916-SS0I-P4LT-SWM6-WXX3LWSJKCVR-low.pngFunctional Block Diagram