CD54HCT573

ACTIVE

High Speed CMOS Logic Octal Transparent Latch with 3-State Output

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Product details

Parameters

Channels (#) 8 Technology Family HCT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Input type TTL-Compatible CMOS Output type 3-State Clock Frequency (Max) (MHz) 25 IOL (Max) (mA) 6 IOH (Max) (mA) -6 ICC (Max) (uA) 160 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Flow-through pinout open-in-new Find other D-type latch

Package | Pins | Size

CDIP (J) 20 167 mm² 26.92 x 7.62 open-in-new Find other D-type latch

Features

  • 4.5-V to 5.5-V VCC Operation
  • Wide Operating Temperature Range of –55°C to 125°C
  • Balanced Propagation Delays and Transition Times
  • Standard Outputs Drive Up to 10 LS-TTL Loads
  • Significant Power Reduction Compared to LS-TTL Logic ICs
  • Inputs Are TTL-Voltage Compatible
open-in-new Find other D-type latch

Description

The 'HCT573 devices are octal transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.

A buffered output-enable (OE\) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

open-in-new Find other D-type latch
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet CD54HCT573, CD74HCT573 datasheet (Rev. C) May 17, 2004
* SMD CD54HCT573 SMD 5962-86856 Jun. 21, 2016
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

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CDIP (J) 20 View options

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