SCHS371G
November 2009 – November 2022
CDC3RL02
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Device Comparison
6
Pin Configuration and Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Low Additive Noise
8.3.2
Regulated 1.8-V Externally Available I/O Supply
8.3.3
Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP Package
8.4
Device Functional Modes
9
Application and Implementation
9.1
Application Information
9.1.1
Input Clock Squarer
9.1.2
Output Stage
9.1.3
LDO
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.3
Application Curve
9.3
Power Supply Recommendations
9.4
Layout
9.4.1
Layout Guidelines
9.4.2
Layout Example
10
Device and Documentation Support
10.1
Receiving Notification of Documentation Updates
10.2
Support Resources
10.3
Trademarks
10.4
Electrostatic Discharge Caution
10.5
Glossary
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
YFP|8
MXBG057R
Thermal pad, mechanical data (Package|Pins)
Orderable Information
schs371g_oa
schs371g_pm
1
Features
Low Additive Noise:
–149 dBc/Hz at 10-kHz Offset Phase Noise
0.37 ps (RMS) Output Jitter
Limited Output Slew Rate for EMI Reduction
(1- to 5-ns Rise/Fall Time for 10-pF to 50-pF Loads)
Adaptive Output Stage Controls Reflection
Regulated 1.8-V Externally Available I/O Supply
Ultra-Small 8-bump YFP 0.4-mm Pitch WCSP
(0.8 mm × 1.6 mm)
ESD Performance Exceeds JESD 22
2000-V Human-Body Model (A114-A)
1000-V Charged-Device Model
(JESD22-C101-A Level III)