SCHS371G November 2009 – November 2022 CDC3RL02
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
LDO | |||||||
VOUT | LDO output voltage | IOUT = 50 mA | 1.71 | 1.8 | 1.89 | V | |
CLDO | External load capacitance | 1 | 10 | μF | |||
IOUT(SC) | Short circuit output current | RL = 0 Ω | 100 | mA | |||
IOUT(PK) | Peak output current | VBATT = 2.3 V, VLDO = VOUT – 5% | 100 | mA | |||
PSR | Power supply rejection | VBATT = 2.3 V, IOUT = 2 mA, | fIN= 217 Hz and 1 kHz | 60 | dB | ||
fIN= 3.25 MHz | 40 | ||||||
tsu | LDO startup time | VBATT = 2.3 V , CLDO = 1 μF, CLK_REQ_n to VIH = 1.71 V | 0.2 | ms | |||
VBATT = 5.5 V , CLDO = 10 μF, CLK_REQ_n to VIH = 1.71 V | 1 | ||||||
POWER CONSUMPTION | |||||||
ISB | Standby current | Device in standby (all VCLK_REQ_n = 0 V) | 0.2 | 1 | μA | ||
ICCS | Static current consumption | Device active but not switching | 0.4 | 1 | mA | ||
IOB | Output buffer average current | fIN = 26 MHz, CLOAD = 50 pF | 4.2 | mA | |||
CPD | Output power dissipation capacitance | fIN = 26 MHz | 44 | pF | |||
MCLK_IN INPUT | |||||||
II | MCLK_IN, CLK_REQ_1/2 leakage current | VI = VIH or GND | 1 | μA | |||
CI | MCLK_IN capacitance | fIN = 26 MHz | 4.75 | pF | |||
RI | MCLK_IN impedance | fIN = 26 MHz | 6 | kΩ | |||
fIN | MCLK_IN frequency range | 10 | 26 | 80 | MHz | ||
MCLK_IN LVCMOS SOURCE | |||||||
Additive phase noise | fIN = 26 MHz, tr/tf ≤ 1 ns | 1-kHz offset | –140 | dBc/Hz | |||
10-kHz offset | –149 | ||||||
100-kHz offset | –153 | ||||||
1-MHz offset | –148 | ||||||
Additive jitter | fIN = 26 MHz, VPP = 0.8 V, BW = 10–5 MHz | 0.37 | ps (rms) | ||||
tDL | MCLK_IN to CLK_OUT_n propagation delay | 11 | ns | ||||
DCL | Output duty cycle | fIN = 26 MHz, DCIN = 50% | 45% | 50% | 55% | ||
MCLK_IN SINUSOIDAL SOURCE | |||||||
VMA | Input amplitude | 0.3 | 1.8 | V | |||
Additive phase noise | fIN = 26 MHz, VMA = 1.8 VPP | 1-kHz offset | –141 | dBc/Hz | |||
10-kHz offset | –149 | ||||||
100-kHz offset | –152 | ||||||
1-MHz offset | –148 | ||||||
fIN = 26 MHz, VMA = 0.8 VPP | 1-kHz offset | –139 | |||||
10-kHz offset | –146 | ||||||
100-kHz offset | –150 | ||||||
1-MHz offset | –146 | ||||||
Additive jitter | fIN = 26 MHz, VMA = 1.8 VPP, BW = 10–5 MHz | 0.41 | ps (RMS) | ||||
tDS | MCLK_IN to CLK_OUT_1/2 propagation delay | 12 | ns | ||||
DCs | Output duty cycle | fIN = 26 MHz, VMA > 1.8 VPP | 45% | 50% | 55% | ||
CLK_OUT_N OUTPUTS | |||||||
tr | 20% to 80% rise time | CL = 10 pF to 50 pF | 1 | 5.2 | ns | ||
tf | 20% to 80% fall time | CL = 10 pF to 50 pF | 1 | 5.2 | ns | ||
tsk | Channel-to-channel skew | CL = 10 pF to 50 pF (CL1 = CL2) | –0.5 | 0.5 | ns | ||
VOH | High-level output voltage | IOH = –100 μA, reference to VLDO | –0.1 | V | |||
IOH = –8 mA | 1.2 | ||||||
VOL | Low-level output voltage | IOL = 20 μA | 0.2 | V | |||
IOL = 8 mA | 0.55 |