The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.
The CDCEx949 has separate output supply pins, VDDOUT, 1.8 V for the CDCEL949, and 2.5 V to 3.3 V for CDCE949.
The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.
||BODY SIZE (NOM)
||7.80 mm × 4.40 mm
- For all available packages, see the orderable addendum at the end of the data sheet.
Typical Application Schematic
4 Revision History
Changes from E Revision (August 2016) to F Revision
Changed data sheet title from: CDCEx949 Programmable 4-PLL VCXO Clock Synthesizer With 1.8-V, 2.5-V, and 3.3-V LVCMOS Outputs to: CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI ReductionGo
Changes from D Revision (March 2010) to E Revision
Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information sectionGo
Condensed down bullets in FeaturesGo
Deleted 'General Purpose Frequency Synthesizing' from ApplicationsGo
Updated values in the Thermal Information table to align with JEDEC standards Go
Changed Byte Read Protocol image, second S to SrGo
Changed 100 MHz < ƒVCO > 200 MHz; TO 80 MHz ≤ ƒVCO ≤ 230 MHz; and changed 0 ≤ p ≤ 7 TO 0 ≤ p ≤ 4Go
Changed under Example, fifth row, N", 2 places TO N'Go
Changes from C Revision (October 2009) to D Revision
Added PLL settings limits: 16 ≤ q ≤ 63, 0 ≤ p ≤ 7, 0 ≤ r ≤ 511, 0 < N < 4096 foot to PLL1, PLL2, PLL3, & PLL4 Configure Register TableGo
Changes from B Revision (September 2009) to C Revision
Deleted sentence - A different default setting can be programmed on customer request. Contact Texas Instruments sales or marketing representative for more information.Go
Changes from A Revision (December 2007) to B Revision
Added Note 3: SDA and SCL can go up to 3.6 V as stated in the Recommended Operating Conditions tableGo
Changes from * Revision (August 2007) to A Revision
Changed the THERMAL RESISTANCE FOR TSSOP tableGo
Changed Generic Configuration Register table RID From: 0h To: XbGo
Added note to the PWDN description, Generic Configuration Register tableGo