Product details

Function Clock synthesizer Number of outputs 9 Output frequency (Max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 2.5, 3.3 Input type XTAL, LVCMOS Output type LVCMOS Operating temperature range (C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
Function Clock synthesizer Number of outputs 9 Output frequency (Max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 2.5, 3.3 Input type XTAL, LVCMOS Output type LVCMOS Operating temperature range (C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
TSSOP (PW) 24 34 mm² 4.4 x 7.8
  • Member of Programmable Clock Generator Family
    • CDCEx913: 1 PLLs, 3 Outputs
    • CDCEx925: 2 PLLs, 5 Outputs
    • CDCEx937: 3 PLLs, 7 Outputs
    • CDCEx949: 4 PLLs, 9 Outputs
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer Settings
  • Flexible Input Clocking Concept
    • External Crystal: 8 to 32 MHz
    • On-Chip VCXO: Pull-Range ±150 ppm
    • Single-Ended LVCMOS Up to 160 MHz
  • Free Selectable Output Frequency Up to 230 MHz
  • Low-Noise PLL Core
    • PLL Loop Filter Components Integrated
    • Low Period Jitter (Typical 60 ps)
  • Separate Output Supply Pins
    • CDCE949: 3.3 V and 2.5 V
    • CDCEL949: 1.8 V
  • Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2], for Example, SSC Selection, Frequency Switching, Output Enable or Power Down
    • Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth®, WLAN, Ethernet™, and GPS
    • Generates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • 1.8-V Device Core Supply
  • Wide Temperature Range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)
  • Member of Programmable Clock Generator Family
    • CDCEx913: 1 PLLs, 3 Outputs
    • CDCEx925: 2 PLLs, 5 Outputs
    • CDCEx937: 3 PLLs, 7 Outputs
    • CDCEx949: 4 PLLs, 9 Outputs
  • In-System Programmability and EEPROM
    • Serial Programmable Volatile Register
    • Nonvolatile EEPROM to Store Customer Settings
  • Flexible Input Clocking Concept
    • External Crystal: 8 to 32 MHz
    • On-Chip VCXO: Pull-Range ±150 ppm
    • Single-Ended LVCMOS Up to 160 MHz
  • Free Selectable Output Frequency Up to 230 MHz
  • Low-Noise PLL Core
    • PLL Loop Filter Components Integrated
    • Low Period Jitter (Typical 60 ps)
  • Separate Output Supply Pins
    • CDCE949: 3.3 V and 2.5 V
    • CDCEL949: 1.8 V
  • Flexible Clock Driver
    • Three User-Definable Control Inputs [S0/S1/S2], for Example, SSC Selection, Frequency Switching, Output Enable or Power Down
    • Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth®, WLAN, Ethernet™, and GPS
    • Generates Common Clock Frequencies Used With TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC Modulation
    • Enables 0-PPM Clock Generation
  • 1.8-V Device Core Supply
  • Wide Temperature Range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and Programming Kit for Easy PLL Design and Programming (TI Pro-Clock™)

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins, VDDOUT, 1.8 V for the CDCEL949, and 2.5 V to 3.3 V for CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of zero-ppm audio or video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27 MHz.

All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. It is preset to a factory-default configuration. It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.

The CDCEx949 operates in a 1.8-V environment. It operates within a temperature range of –40°C to 85°C.

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. They generate up to 9 output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins, VDDOUT, 1.8 V for the CDCEL949, and 2.5 V to 3.3 V for CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 to 20 pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of zero-ppm audio or video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27 MHz.

All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. It is preset to a factory-default configuration. It can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.

The CDCEx949 operates in a 1.8-V environment. It operates within a temperature range of –40°C to 85°C.

Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 15
Type Title Date
* Data sheet CDCE(L)913: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet (Rev. F) 27 Oct 2016
Technical article The five benefits of multifaceted clocking devices 17 May 2016
Technical article How to select an optimal clocking solution for your FPGA-based design 09 Dec 2015
Technical article Clocking sampled systems to minimize jitter 31 Jul 2014
Technical article Timing is Everything: How to optimize clock distribution in PCIe applications 28 Mar 2014
Application note VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) 23 Apr 2012
User guide CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) 22 Nov 2010
User guide CDCE(L)9xx Performance Evaluation Module (Rev. A) 07 Jul 2010
Application note General I2C / EEPROM usage for the CDCE(L)9xx family 26 Jan 2010
Application note Troubleshooting I2C Bus Protocol 19 Oct 2009
Application note Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 23 Sep 2009
User guide CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual 09 Dec 2008
Application note Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency 31 Mar 2008
Application note Practical consideration on choosing a crystal for CDCE(L)9xx family 24 Mar 2008
Application note Clocking Recommendations for DM6446 Digital Video EVM with Sngle PLL (Rev. A) 08 Aug 2007

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCE949PERF-EVM — CDCE949 Performance Evaluation Module

The CDCE949Perf-Evaluation Module will help to verify the functionality and performance of CDCE949 with the options of crystal and 1.8 V LVCMOS inputs. The outputs can be connected to the Oscilloscope directly with SMA cables. The below information/items can be included The EVM use’s (...)

In stock
Limit: 2
Evaluation board

CDCEL9XXPROGEVM — CDCE(L)949 Family EEPROM Programming Board

The clock generator CDCE(L)949 family has integrated EEPROM that allows the default frequency settings to be saved upon start up. CDCEL9XXPROGEVM is a programming board that allows a fast programming of prototyping samples or small production quantities. It applies to all 8 devices in the family: (...)

In stock
Limit: 2
Driver or library

Drivers for the CDCEL9xx programmer EVM

SCAC131.ZIP (77 KB)
GUI for evaluation module (EVM)

TI-Pro-Clock Programming Software (Rev. F)

SCAC073F.ZIP (88940 KB)
Software programming tool

CLOCKPRO — ClockPro™ Programming Software

TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:
  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

Support software

ClockPro Software (Rev. E)

SCAC119E.ZIP (4405 KB)
Simulation model

CDCE949 IBIS Model (Rev. B)

SCAC094B.ZIP (42 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
Reference designs

TIDA-010057 — Ultrasound smart probe power supply reference design

Significant technological advancements and high degree of integration in Medical imaging, especially hand-held ultrasound smart probes, are pushing engineers to come up with highly-efficient, noise immune power solutions in a small size. This reference design documents end to end power and data (...)
Package Pins Download
TSSOP (PW) 24 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos