SLPS392D March   2013  – November 2017 CSD17556Q5B

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Receiving Notification of Documentation Updates
    2. 6.2 Community Resources
    3. 6.3 Trademarks
    4. 6.4 Electrostatic Discharge Caution
    5. 6.5 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Q5B Package Dimensions
    2. 7.2 Recommended PCB Pattern
    3. 7.3 Recommended Stencil Pattern
    4. 7.4 Q5B Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DNK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 μA 1.15 1.4 1.65 V
RDS(on) Drain-to-source on-resistance VGS = 4.5 V, IDS = 40 A 1.5 1.8 mΩ
VGS = 10 V, IDS = 40 A 1.2 1.4
gfs Transconductance VDS = 15 V, IDS = 40 A 197 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 5400 7020 pF
Coss Output capacitance 1770 2310 pF
Crss Reverse transfer capacitance 68 88 pF
RG Series gate resistance 0.7 1.4 Ω
Qg Gate charge total (4.5 V) VDS = 15 V, IDS = 40 A 30 39 nC
Qgd Gate charge gate-to-drain 7.5 nC
Qgs Gate charge gate-to-source 11 nC
Qg(th) Gate charge at Vth 6.1 nC
Qoss Output charge VDS = 15 V, VGS = 0 V 48 nC
td(on) Turnon delay time VDS = 15 V, VGS = 4.5 V,
IDS = 40 A, RG = 2 Ω		 14 ns
tr Rise time 26 ns
td(off) Turnoff delay time 27 ns
tf Fall time 12 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 40 A, VGS = 0 V 0.8 1 V
Qrr Reverse recovery charge VDD= 15 V, IF = 40 A, di/dt = 300 A/μs 68 nC
trr Reverse recovery time 36 ns

5.2 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance(1) 1.3 °C/W
RθJA Junction-to-ambient thermal resistance(1)(2) 50
(1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.

CSD17556Q5B M0137-01_LPS198.gif
Max RθJA = 50°C/W when mounted on 1-in2 (6.45-cm2) of
2-oz (0.071-mm) thick Cu.
CSD17556Q5B M0137-02_LPS198.gif
Max RθJA = 125°C/W when mounted on a minimum pad area of
2-oz (0.071-mm) thick Cu.

5.3 Typical MOSFET Characteristics

TA = 25°C (unless otherwise stated)
CSD17556Q5B graph01_SLPS392B.png
Figure 1. Transient Thermal Impedance
CSD17556Q5B graph02_SLPS392F.png
Figure 2. Saturation Characteristics
CSD17556Q5B graph04_SLPS392F.png
Figure 4. Gate Charge
CSD17556Q5B graph06_SLPS392F.png
Figure 6. Threshold Voltage vs Temperature
CSD17556Q5B graph08_SLPS392F.png
Figure 8. Normalized On-State Resistance vs Temperature
CSD17556Q5B graph10_SLPS392B.png
Figure 10. Maximum Safe Operating Area (SOA)
CSD17556Q5B graph12_SLPS392F.png
Figure 12. Maximum Drain Current vs Temperature
CSD17556Q5B graph03_SLPS392F.png
Figure 3. Transfer Characteristics
CSD17556Q5B graph05_SLPS392F.png
Figure 5. Capacitance
CSD17556Q5B graph07_SLPS392F.png
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD17556Q5B graph09_SLPS392F.png
Figure 9. Typical Diode Forward Voltage
CSD17556Q5B graph11_SLPS392F.png
Figure 11. Single Pulse Unclamped Inductive Switching