SLPS444C July   2013  – January 2016 CSD18563Q5A

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Community Resources
    2. 6.2 Trademarks
    3. 6.3 Electrostatic Discharge Caution
    4. 6.4 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Q5A Package Dimensions
    2. 7.2 Recommended PCB Pattern
    3. 7.3 Recommended Stencil Opening
    4. 7.4 Q5A Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQJ|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Electrical Characteristics

(TA = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 60 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 48 V 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 1.7 2.0 2.4 V
RDS(on) Drain-to-source on resistance VGS = 4.5 V, ID = 18 A 8.6 10.8 mΩ
VGS = 10 V, ID = 18 A 5.7 6.8 mΩ
gfs Transconductance VDS = 30 V, ID = 18 A 60 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 30 V, ƒ = 1 MHz 1150 1500 pF
Coss Output capacitance 280 364 pF
Crss Reverse transfer capacitance 3.9 5.1 pF
RG Series gate resistance 1.5 3.0 Ω
Qg Gate charge total (4.5 V) VDS = 30 V, ID = 18 A 7.3 9.5 nC
Qg Gate charge total (10 V) 15 20
Qgd Gate charge gate-to-drain 2.9 nC
Qgs Gate charge gate-to-source 3.3 nC
Qg(th) Gate charge at Vth 2.3 nC
Qoss Output charge VDS = 30 V, VGS = 0 V 36 nC
td(on) Turn on delay time VDS = 30 V, VGS = 10 V, IDS = 18 A, RG = 0 Ω 3.2 ns
tr Rise time 6.3 ns
td(off) Turn off delay time 11.4 ns
tf Fall time 1.7 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 18 A, VGS = 0 V 0.8 1 V
Qrr Reverse recovery charge VDS= 30 V, IF = 18 A, di/dt = 300 A/μs 63 nC
trr Reverse recovery time 49 ns

5.2 Thermal Information

(TA = 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance(1) 1.3 °C/W
RθJA Junction-to-ambient thermal resistance(1)(2) 50
(1) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
CSD18563Q5A M0137-01_LPS198.gif
Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick) Cu.
CSD18563Q5A M0137-02_LPS198.gif
Max RθJA = 125°C/W when mounted on a minimum pad area of
2 oz. (0.071 mm thick) Cu.

5.3 Typical MOSFET Characteristics

(TA = 25°C unless otherwise stated)
CSD18563Q5A graph01_SLPS444B.png
Figure 1. Transient Thermal Impedance
CSD18563Q5A graph02p2_SLPS444.png
Figure 2. Saturation Characteristics
CSD18563Q5A graph04_SLPS444.png
Figure 4. Gate Charge
CSD18563Q5A graph06_SLPS444.png
Figure 6. Threshold Voltage vs Temperature
CSD18563Q5A graph08p2_SLPS444.png
Figure 8. Normalized On-State Resistance vs Temperature
CSD18563Q5A graph10_SLPS444B.png
Figure 10. Maximum Safe Operating Area
CSD18563Q5A graph12_SLPS444.png
Figure 12. Maximum Drain Current vs Temperature
CSD18563Q5A graph03p2_SLPS444.png
Figure 3. Transfer Characteristics
CSD18563Q5A graph05_SLPS444.png
Figure 5. Capacitance
CSD18563Q5A graph07p2_SLPS444.png
Figure 7. On-State Resistance vs Gate-To-Source Voltage
CSD18563Q5A graph09_SLPS444.png
Figure 9. Typical Diode Forward Voltage
CSD18563Q5A graph11_SLPS444.png
Figure 11. Single Pulse Unclamped Inductive Switching