SLPS406B September   2013  – May 2014 CSD19531Q5A

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Characteristics
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Trademarks
    2. 6.2 Electrostatic Discharge Caution
    3. 6.3 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Q5A Package Dimensions
    2. 7.2 Recommended PCB Pattern
    3. 7.3 Recommended Stencil Opening
    4. 7.4 Q5A Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQJ|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Electrical Characteristics

(TA = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA 100 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 80 V 1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA 2.2 2.7 3.3 V
RDS(on) Drain-to-Source On Resistance VGS = 6 V, ID = 16 A 6.0 7.8
VGS = 10 V, ID = 16 A 5.3 6.4
gfs Transconductance VDS = 10 V, ID = 16 A 82 S
DYNAMIC CHARACTERISTICS
Ciss Input Capacitance VGS = 0 V, VDS = 50 V, ƒ = 1 MHz 2980 3870 pF
Coss Output Capacitance 560 728 pF
Crss Reverse Transfer Capacitance 13.0 16.9 pF
RG Series Gate Resistance 1.3 2.6 Ω
Qg Gate Charge Total (10 V) VDS = 50 V, ID = 16 A 37 48 nC
Qgd Gate Charge Gate to Drain 6.6 nC
Qgs Gate Charge Gate to Source 10.5 nC
Qg(th) Gate Charge at Vth 7.3 nC
Qoss Output Charge VDS = 50 V, VGS = 0 V 97 nC
td(on) Turn On Delay Time VDS = 50 V, VGS = 10 V,
IDS = 16 A, RG = 0 Ω
6.0 ns
tr Rise Time 5.8 ns
td(off) Turn Off Delay Time 18.4 ns
tf Fall Time 5.2 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage ISD = 16 A, VGS = 0 V 0.8 1 V
Qrr Reverse Recovery Charge VDS= 50 V, IF = 16 A,
di/dt = 300 A/μs
226 nC
trr Reverse Recovery Time 148 ns

5.2 Thermal Characteristics

(TA = 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-Case Thermal Resistance(1) 1 °C/W
RθJA Junction-to-Ambient Thermal Resistance(1)(2) 50
(1) RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
M0137-01_LPS198.gif
Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick) Cu.
M0137-02_LPS198.gif
Max RθJA = 115°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu.

5.3 Typical MOSFET Characteristics

(TA = 25°C unless otherwise stated)
graph01_SLPS406B.png
Figure 1. Transient Thermal Impedance
graph02_SLPS406.png
Figure 2. Saturation Characteristics
graph04_SLPS406.png
Figure 4. Gate Charge
graph06_SLPS406.png
Figure 6. Threshold Voltage vs Temperature
graph08_SLPS406.png
Figure 8. Normalized On-State Resistance vs Temperature
graph10_SLPS406B.png
Figure 10. Maximum Safe Operating Area
graph12_SLPS406.png
Figure 12. Maximum Drain Current vs Temperature
graph03_SLPS406.png
Figure 3. Transfer Characteristics
graph05_SLPS406.png
Figure 5. Capacitance
graph07_SLPS406.png
Figure 7. On-State Resistance vs Gate-To-Source Voltage
graph09_SLPS406.png
Figure 9. Typical Diode Forward Voltage
graph11_SLPS406.png
Figure 11. Single Pulse Unclamped Inductive Switching