SLPS549A August   2015  – May 2016 CSD19537Q3

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Community Resources
    2. 6.2 Trademarks
    3. 6.3 Electrostatic Discharge Caution
    4. 6.4 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Q3 Package Dimensions
    2. 7.2 Recommended PCB Pattern
    3. 7.3 Recommended Stencil Opening
    4. 7.4 Q3 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQG|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 100 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 80 V 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 2.6 3 3.6 V
RDS(on) Drain-to-source on-resistance VGS = 6 V, ID = 10 A 13.8 16.6
VGS = 10 V, ID = 10 A 12.1 14.5
gfs Transconductance VDS = 10 V, ID = 10 A 45 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 50 V, ƒ = 1 MHz 1290 1680 pF
Coss Output capacitance 251 326 pF
Crss Reverse transfer capacitance 13.3 17.3 pF
RG Series gate resistance 1.2 2.4 Ω
Qg Gate charge total (10 V) VDS = 50 V, ID = 10 A 16 21 nC
Qgd Gate charge gate-to-drain 2.9 nC
Qgs Gate charge gate-to-source 5.5 nC
Qg(th) Gate charge at Vth 3.8 nC
Qoss Output charge VDS = 50 V, VGS = 0 V 44 nC
td(on) Turn on delay time VDS = 50 V, VGS = 10 V,
IDS = 10 A, RG = 0 Ω
5 ns
tr Rise time 3 ns
td(off) Turn off delay time 10 ns
tf Fall time 3 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 10 A, VGS = 0 V 0.8 1 V
Qrr Reverse recovery charge VDS= 50 V, IF = 10 A,
di/dt = 300 A/μs
134 nC
trr Reverse recovery time 36 ns

5.2 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJC Junction-to-case thermal resistance(1) 1.5 °C/W
RθJA Junction-to-ambient thermal resistance(1)(2) 55 °C/W
(1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
CSD19537Q3 m0161-01_lps202.gif
Max RθJA = 55°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu.
CSD19537Q3 m0161-02_lps202.gif
Max RθJA = 160°C/W when mounted on a minimum pad area of 2-oz (0.071-mm) thick Cu.

5.3 Typical MOSFET Characteristics

TA = 25°C (unless otherwise stated)
CSD19537Q3 D001_SLPS549.png
Figure 1. Transient Thermal Impedance
CSD19537Q3 D002_SLPS549.gif
Figure 2. Saturation Characteristics
CSD19537Q3 D004_SLPS549.gif
ID = 10 A VDS = 50 V
Figure 4. Gate Charge
CSD19537Q3 D006_SLPS549.gif
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
CSD19537Q3 D008_SLPS549.gif
ID = 10 A
Figure 8. Normalized On-State Resistance vs Temperature
CSD19537Q3 D010_SLPS549.gif
Single Pulse, Max RθJC = 1.5°C/W
Figure 10. Maximum Safe Operating Area
CSD19537Q3 D012_SLPS549.gif
Figure 12. Maximum Drain Current vs Temperature
CSD19537Q3 D003_SLPS549.gif
VDS = 5 V
Figure 3. Transfer Characteristics
CSD19537Q3 D005_SLPS549_r2.gif
Figure 5. Capacitance
CSD19537Q3 D007_SLPS549.gif
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD19537Q3 D009_SLPS549.gif
Figure 9. Typical Diode Forward Voltage
CSD19537Q3 D011_SLPS549_r2.gif
Figure 11. Single Pulse Unclamped Inductive Switching