SLPS575A March   2016  – September 2017 CSD87355Q5D

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Handling Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Power Block Performance
    6. 5.6 Electrical Characteristics
    7. 5.7 Typical Power Block Device Characteristics
    8. 5.8 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Equivalent System Performance
      2. 6.1.2 Power Loss Curves
      3. 6.1.3 Safe Operating Curves (SOA)
      4. 6.1.4 Normalized Curves
    2. 6.2 Typical Application
      1. 6.2.1 Design Example: Calculating Power Loss and SOA
      2. 6.2.2 Operating Conditions
        1. 6.2.2.1 Calculating Power Loss
        2. 6.2.2.2 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Considerations
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Community Resources
    2. 8.2 Trademarks
    3. 8.3 Electrostatic Discharge Caution
    4. 8.4 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Q5D Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQY|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted)(1)
MIN MAX UNIT
Voltage VIN to PGND –0.8 30 V
TG to TGR –8 10 V
BG to PGND –8 10 V
Pulsed current rating, IDM(2) 120 A
Power dissipation, PD 12 W
Avalanche energy EAS Sync FET, ID = 89 A, L = 0.1 mH 396 mJ
Control FET, ID = 50 A, L = 0.1 mH 125 mJ
Operating junction temperature, TJ –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse duration ≤ 50 µS. Duty cycle ≤ 0.01.

5.2 Handling Ratings

MIN MAX UNIT
Tstg Storage temperature range –55 150 °C

5.3 Recommended Operating Conditions

TA = 25° (unless otherwise noted)
MIN MAX UNIT
VGS Gate drive voltage 4.5 10 V
VIN Input supply voltage 27 V
ƒSW Switching frequency CBST = 0.1 μF (min) 200 1500 kHz
Operating current 45 A
TJ Operating temperature 125 °C

5.4 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (min Cu)(1)(2) 102 °C/W
Junction-to-ambient thermal resistance (max Cu)(1)(2) 50 °C/W
RθJC Junction-to-case thermal resistance (top of package)(2) 20 °C/W
Junction-to-case thermal resistance (PGND pin)(2) 2 °C/W
(1) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu.
(2) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.

5.5 Power Block Performance

TA = 25° (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power loss, PLOSS(1) VIN = 12 V, VGS = 5 V, VOUT = 1.3 V,
IOUT = 25 A, ƒSW = 500 kHz,
LOUT = 0.29 µH, TJ = 25ºC		 2.8 W
VIN quiescent current, IQVIN TG to TGR = 0 V ,BG to PGND = 0 V 10 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5 V driver IC.

5.6 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 CONTROL FET Q2 SYNC FET UNIT
MIN TYP MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA 30 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 1 μA
IGSS Gate-to-source leakage current VDS = 0 V,
VGS = +10 / –8 V		 100 100 nA
VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 μA 1.00 1.90 0.75 1.20 V
ZDS(ON)(1) Drain-to-source ON impedance VIN = 12 V, VGS = 5 V, VOUT = 1.3 V, IOUT = 25 A, ƒSW = 500 kHz,
LOUT = 0.29 µH		 3.9 0.9 mΩ
gfs Transconductance VDS = 3 V, IDS = 20 A 90 151 S
DYNAMIC CHARACTERISTICS
CISS Input capacitance VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 1430 1860 3570 4640 pF
COSS Output capacitance 716 930 1730 2240 pF
CRSS Reverse transfer capacitance 25 32 52 67 pF
RG Series gate resistance 0.6 1.2 0.7 1.4 Ω
Qg Gate charge total (4.5 V) VDS = 15 V,
IDS = 20 A		 10.5 13.7 24.3 31.5 nC
Qgd Gate charge – gate-to-drain 2.3 4.1 nC
Qgs Gate charge – gate-to-source 3.2 5.6 nC
Qg(th) Gate charge at Vth 1.7 2.8 nC
QOSS Output charge VDS = 15 V, VGS = 0 V 18 40 nC
td(on) Turn on delay time VDS = 15 V, VGS = 4.5 V,
IDS = 20 A, RG = 2 Ω		 8 10 ns
tr Rise time 18 14 ns
td(off) Turn off delay time 13 27 ns
tf Fall time 3 6 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage IDS = 20 A, VGS = 0 V 0.8 1.0 0.8 1.0 V
Qrr Reverse recovery charge Vdd = 17 V, IF = 20 A,
di/dt = 300 A/μs		 43 82 nC
trr Reverse recovery time 23.8 32.3 ns
(1) Equivalent based on application testing. See Application and Implementation section for details.

CSD87355Q5D M0189-01_LPS293.gif
Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of
2 oz. (0.071-mm thick) Cu.
CSD87355Q5D M0190-01_LPS293.gif
Max RθJA = 102°C/W when mounted on minimum pad area of
2 oz. (0.071-mm thick) Cu.

5.7 Typical Power Block Device Characteristics

TJ = 125°C, unless stated otherwise. The Typical Power Block System Characteristic curves Figure 3, , and Figure 4 are based on measurements made on a PCB design with dimensions of 4” (W) × 3.5” (L) × 0.062” (H) and 6 copper layers of 1-oz. copper thickness. See Application and Implementation for detailed explanation.
CSD87355Q5D D001_SLPS575.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 1. Power Loss vs Output Current
CSD87355Q5D D003_SLPS575.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 3. Safe Operating Area (SOA) – Thermal Airflow Measurement PCB Vertical Mount
CSD87355Q5D D006_SLPS575_r2.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
LOUT = 0.29 µH IOUT = 45 A
Figure 5. Normalized Power Loss vs Switching Frequency
CSD87355Q5D D008_SLPS575_r2.gif
VIN = 12 V VGS = 5 V ƒSW = 500 kHz
LOUT = 0.29 µH IOUT = 45 A
Figure 7. Normalized Power Loss vs. Output Voltage
CSD87355Q5D D002_SLPS575.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 2. Normalized Power Loss vs Temperature
CSD87355Q5D D005_SLPS575.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
ƒSW = 500 kHz LOUT = 0.29 µH
Figure 4. Typical Safe Operating Area (SOA)
CSD87355Q5D D007_SLPS575.gif
VIN = 12 V VOUT = 1.3 V LOUT = 0.29 µH
ƒSW = 500 kHz IOUT = 45 A
Figure 6. Normalized Power Loss vs Input Voltage
CSD87355Q5D D009_SLPS575.gif
VIN = 12 V VGS = 5 V VOUT = 1.3 V
ƒSW = 500 kHz IOUT = 45 A
Figure 8. Normalized Power Loss vs Output Inductance

5.8 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD87355Q5D D010_SLPS575_r2.gif
Figure 9. Control MOSFET Saturation
CSD87355Q5D D012_SLPS575.gif
VDS = 5 V
Figure 11. Control MOSFET Transfer
CSD87355Q5D D014_SLPS575.gif
ID = 20 A VDD = 15 V
Figure 13. Control MOSFET Gate Charge
CSD87355Q5D D016_SLPS575.gif
ƒ = 1 MHz VGS = 0
Figure 15. Control MOSFET Capacitance
CSD87355Q5D D018_SLPS575.gif
ID = 250 µA
Figure 17. Control MOSFET VGS(th)
CSD87355Q5D D020_SLPS575_r2.gif
Figure 19. Control MOSFET RDS(ON) vs VGS
CSD87355Q5D D022_SLPS575.gif
ID = 20 A VGS = 8 V
Figure 21. Control MOSFET Normalized RDS(ON)
CSD87355Q5D D024_SLPS575.gif
Figure 23. Control MOSFET Body Diode
CSD87355Q5D D026_SLPS575_r2.gif
Figure 25. Control MOSFET Unclamped Inductive Switching
CSD87355Q5D D011_SLPS575_r2.gif
Figure 10. Sync MOSFET Saturation
CSD87355Q5D D013_SLPS575.gif
VDS = 5 V
Figure 12. Sync MOSFET Transfer
CSD87355Q5D D015_SLPS575.gif
ID = 20 A VDD = 15 V
Figure 14. Sync MOSFET Gate Charge
CSD87355Q5D D017_SLPS575.gif
ƒ = 1 MHz VGS = 0
Figure 16. Sync MOSFET Capacitance
CSD87355Q5D D019_SLPS575.gif
ID = 250 µA
Figure 18. Sync MOSFET VGS(th)
CSD87355Q5D D021_SLPS575_r2.gif
Figure 20. Sync MOSFET RDS(ON) vs VGS
CSD87355Q5D D023_SLPS575.gif
ID = 20 A VGS = 8 V
Figure 22. Sync MOSFET Normalized RDS(ON)
CSD87355Q5D D025_SLPS575.gif
Figure 24. Sync MOSFET Body Diode
CSD87355Q5D D027_SLPS575_r2.gif
Figure 26. Sync MOSFET Unclamped Inductive Switching