SLPS415D September   2013  – March 2015 CSD87384M

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Power Block Performance
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Power Loss Curves
    3. 6.3 Safe Operating Curves (SOA)
    4. 6.4 Normalized Curves
    5. 6.5 Calculating Power Loss and SOA
      1. 6.5.1 Design Example
      2. 6.5.2 Calculating Power Loss
      3. 6.5.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Recommended PCB Design Overview
      2. 7.1.2 Electrical Performance
      3. 7.1.3 Thermal Performance
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Trademarks
    2. 8.2 Electrostatic Discharge Caution
    3. 8.3 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 CSD87384M Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation (100 µm)
    4. 9.4 Stencil Recommendation (125 µm)
    5. 9.5 Pin Drawing
    6. 9.6 CSD87384M Embossed Carrier Tape Dimensions

Package Options

Mechanical Data (Package|Pins)
  • MPB|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted) (1)
MIN MAX UNIT
Voltage VIN to PGND –0.8 30 V
VSW to PGND 30
VSW to PGND (10 ns) 32
TG to VSW –8 10
BG to PGND –8 10
IDM Pulsed Current Rating(2) 95 A
PD Power Dissipation(3) 8 W
EAS Avalanche Energy Sync FET, ID = 68, L = 0.1 mH 231 mJ
Control FET, ID = 31, L = 0.1 mH 48
TJ Operating Junction –55 150 °C
Tstg Storage Temperature Range –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse Duration ≤50 µs, duty cycle ≤0.01
(3) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu

5.2 Recommended Operating Conditions

TA = 25°C (unless otherwise noted)
MIN MAX UNIT
VGS Gate Drive Voltage 4.5 8 V
VIN Input Supply Voltage 24 V
ƒSW Switching Frequency CBST = 0.1 μF (min) 200 1500 kHz
Operating Current No Airflow 30 A
With Airflow (200 LFM) 35 A
With Airflow + Heat Sink 40 A
TJ Operating Temperature 125 °C

5.3 Power Block Performance

TA = 25°C (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PLOSS Power Loss(1) VIN = 12 V, VGS = 5 V
VOUT = 1.3 V, IOUT = 25 A
fSW = 500 kHz
LOUT = 0.3 µH, TJ = 25ºC 		3.7 W
IQVIN VIN Quiescent Current TG to TGR = 0 V
BG to PGND = 0 V 		10 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5 V driver IC.

5.4 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (Min Cu) (2) 153 °C/W
Junction-to-ambient thermal resistance (Max Cu) (1)(2) 67
RθJC Junction-to-case thermal resistance (Top of package) (2) 3.0
Junction-to-case thermal resistance (PGND Pin) (2) 1.25
(1) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu.
(2) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 Control FET Q2 Sync FET UNIT
MIN TYP MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA 30 30 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 10 V 100 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA 1.1 1.9 1.1 1.7 V
RDS(on) Drain-to-Source On-Impedance VGS = 4.5 V, IDS = 25 A 7.5 8.9 2.15 2.6 mΩ
VGS = 8 V, IDS = 25 A 6.4 7.7 1.95 2.4
gƒs Transconductance VDS = 10 V, IDS = 25 A 67 240 S
DYNAMIC CHARACTERISTICS
CISS Input Capacitance (1) VGS = 0 V, VDS = 15 V,
f = 1MHz		 884 1150 3760 4890 pF
COSS Output Capacitance (1) 452 588 1110 1440 pF
CRSS Reverse Transfer Capacitance (1) 19.4 25.2 87 114 pF
RG Series Gate Resistance (1) 1.0 2.0 0.7 1.4 Ω
Qg Gate Charge Total (4.5 V) (1) VDS = 15 V,
IDS = 25 A		 7.1 9.2 31 40 nC
Qgd Gate Charge – Gate-to-Drain 1.5 8.6 nC
Qgs Gate Charge – Gate-to-Source 2.7 8.6 nC
Qg(th) Gate Charge at Vth 1.3 5.4 nC
QOSS Output Charge VDD = 12 V, VGS = 0 V 11.3 37 nC
td(on) Turn On Delay Time VDS = 15 V, VGS = 4.5 V,
IDS = 25 A, RG = 2 Ω		 8.7 17.5 ns
tr Rise Time 56 49 ns
td(off) Turn-Off Delay Time 14 29 ns
tƒ Fall Time 7.6 8.2 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage IDS = 25 A, VGS = 0 V 0.85 0.80 V
Qrr Reverse Recovery Charge Vdd = 15 V, IF = 25 A,
di/dt = 300 A/μs		 21 51 nC
trr Reverse Recovery Time 21 32 ns
(1) Specified by design
CSD87384M Thermal_Max.gif
 Max RθJA = 67°C/W when mounted on 1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick) Cu.
CSD87384M Thermal_Min.gif
 Max RθJA = 153°C/W when mounted on minimum pad area of
2 oz. (0.071 mm thick) Cu.

5.6 Typical Power Block Device Characteristics

TJ = 125°C, unless stated otherwise. For Figure 3 and Figure 4, the Typical Power Block System Characteristic curves are based on measurements made on a PCB design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (H) and 6 copper layers of 1 oz. copper thickness. See Application and Implementation for detailed explanation.
CSD87384M graph01_SLPS415.png
Figure 1. Power Loss vs Output Current
CSD87384M graph03p2_SLPS415.png
Figure 3. Safe Operating Area – PCB Horizontal Mount
CSD87384M graph02_SLPS415.png
Figure 2. Normalized Power Loss vs Temperature
CSD87384M graph04_SLPS415.png
Figure 4. Typical Safe Operating Area
CSD87384M graph05p2_SLPS415.png
Figure 5. Normalized Power Loss vs Switching Frequency
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Figure 7. Normalized Power Loss vs Output Voltage
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Figure 6. Normalized Power Loss vs Input Voltage
CSD87384M graph08_SLPS415.png
Figure 8. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD87384M graph09_SLPS415.png
Figure 9. Control MOSFET Saturation
CSD87384M graph11_SLPS415.png
Figure 11. Control MOSFET Transfer
CSD87384M graph13_SLPS415.png
Figure 13. Control MOSFET Gate Charge
CSD87384M graph15_SLPS415D.png
Figure 15. Control MOSFET Capacitance
CSD87384M graph17_SLPS415.png
Figure 17. Control MOSFET VGS(th)
CSD87384M graph19_SLPS415.png
Figure 19. Control MOSFET RDS(on) vs VGS
CSD87384M graph21_SLPS415.png
Figure 21. Control MOSFET Normalized RDS(on)
CSD87384M graph23_SLPS415.png
Figure 23. Control MOSFET Body Diode
CSD87384M graph25_SLPS415.png
Figure 25. Control MOSFET Unclamped Inductive Switching
CSD87384M graph10_SLPS415.png
Figure 10. Sync MOSFET Saturation
CSD87384M graph12_SLPS415.png
Figure 12. Sync MOSFET Transfer
CSD87384M graph14_SLPS415.png
Figure 14. Sync MOSFET Gate Charge
CSD87384M graph16_SLPS415D.png
Figure 16. Sync MOSFET Capacitance
CSD87384M graph18_SLPS415.png
Figure 18. Sync MOSFET VGS(th)
CSD87384M graph20_SLPS415.png
Figure 20. Sync MOSFET RDS(on) vs VGS
CSD87384M graph22_SLPS415.png
Figure 22. Sync MOSFET Normalized RDS(on)
CSD87384M graph24_SLPS415.png
Figure 24. Sync MOSFET Body Diode
CSD87384M graph26_SLPS415.png
Figure 26. Sync MOSFET Unclamped Inductive Switching