SLPS560 December   2015 CSD87502Q2

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Electrical Characteristics
    2. 5.2 Thermal Information
    3. 5.3 Typical MOSFET Characteristics
  6. 6Device and Documentation Support
    1. 6.1 Community Resources
    2. 6.2 Trademarks
    3. 6.3 Electrostatic Discharge Caution
    4. 6.4 Glossary
  7. 7Mechanical, Packaging, and Orderable Information
    1. 7.1 Package Dimensions
    2. 7.2 PCB Land Pattern
    3. 7.3 Recommended Stencil Opening
    4. 7.4 Q2 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DQK|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Specifications

5.1 Electrical Characteristics

(TA = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC CHARACTERISTICS
BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 30 V
IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 μA
IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 4 μA
VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 1.2 1.6 2.0 V
RDS(on) Drain-to-source on-resistance VGS = 3.8 V, ID = 4 A 42.0 60.0 mΩ
VGS = 4.5 V, ID = 4 A 35.5 42.0 mΩ
VGS = 10 V, ID = 4 A 27.0 32.4 mΩ
gfs Transconductance VDS = 3 V, ID = 4 A 75 S
DYNAMIC CHARACTERISTICS
Ciss Input capacitance VGS = 0 V, VDS = 15 V, ƒ = 1 MHz 272 353 pF
Coss Output capacitance 42 55 pF
Crss Reverse transfer capacitance 22 29 pF
RG Series gate resistance 6.9 Ω
Qg Gate charge total (4.5 V) VDS = 15 V, ID = 4 A 2.2 2.9 nC
Qg Gate charge total (10 V) 4.6 6.0 nC
Qgd Gate charge gate to drain 0.5 nC
Qgs Gate charge gate to source 1.0 nC
Qg(th) Gate charge at Vth 0.5 nC
Qoss Output charge VDS = 15 V, VGS = 0 V 1.4 nC
td(on) Turn on delay time VDS = 15 V, VGS = 5 V,
IDS = 4 A, RG = 0 Ω		 3 ns
tr Rise time 11 ns
td(off) Turn off delay time 12 ns
tf Fall time 3 ns
DIODE CHARACTERISTICS
VSD Diode forward voltage ISD = 4 A, VGS = 0 V 0.85 1.0 V
Qrr Reverse recovery charge VDS= 15 V, IF = 4 A,
di/dt = 300 A/μs		 4.0 nC
trr Reverse recovery time 6.4 ns

5.2 Thermal Information

(TA = 25°C unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance(1) 70 °C/W
Junction-to-ambient thermal resistance(2) 185
(1) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
(2) Device mounted on FR4 material with minimum Cu mounting area.
CSD87502Q2 M0164-01_LPS235.gif
Max RθJA = 70 when mounted on 1 inch2 (6.45 cm2) of 2 oz.
(0.071 mm thick) Cu.
CSD87502Q2 M0164-02_LPS235.gif
Max RθJA = 185 when mounted on minimum pad area of 2 oz.
(0.071 mm thick) Cu.

5.3 Typical MOSFET Characteristics

(TA = 25°C unless otherwise stated)
CSD87502Q2 D001_SLPS560.png
Figure 1. Transient Thermal Impedance
CSD87502Q2 D002_SLPS560.gif
Figure 2. Saturation Characteristics
CSD87502Q2 D004_SLPS560.gif
ID = 4 A VDS = 15 V
Figure 4. Gate Charge
CSD87502Q2 D006_SLPS560.gif
ID = 4 A
Figure 6. Threshold Voltage vs Temperature
CSD87502Q2 D008_SLPS560_r2.gif
ID = 4 A
Figure 8. Normalized On-State Resistance vs Temperature
CSD87502Q2 D010_SLPS560.gif
Single Pulse, Max RθJA = 185°C/W
Figure 10. Maximum Safe Operating Area
CSD87502Q2 D012_SLPS560_r2.gif
Figure 12. Maximum Drain Current vs Temperature
CSD87502Q2 D003_SLPS560.gif
VDS = 5 V
Figure 3. Transfer Characteristics
CSD87502Q2 D005_SLPS560_r2.gif
Figure 5. Capacitance
CSD87502Q2 D007_SLPS560.gif
Figure 7. On-State Resistance vs Gate-to-Source Voltage
CSD87502Q2 D009_SLPS560.gif
Figure 9. Typical Diode Forward Voltage
CSD87502Q2 D011_SLPS560.gif
Figure 11. Single Pulse Unclamped Inductive Switching