SLPS384D March   2013  – April 2015 CSD87588N

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power Loss Curves
      2. 6.1.2 Safe Operating Curves (SOA)
      3. 6.1.3 Normalized Curves
      4. 6.1.4 Calculating Power Loss and SOA
        1. 6.1.4.1 Design Example
        2. 6.1.4.2 Calculating Power Loss
        3. 6.1.4.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Performance
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Trademarks
    2. 8.2 Electrostatic Discharge Caution
    3. 8.3 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 CSD87588N Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation (100 µm)
    4. 9.4 Stencil Recommendation (125 µm)
    5. 9.5 Pin Drawing
    6. 9.6 CSD87588N Embossed Carrier Tape Dimensions

Package Options

Mechanical Data (Package|Pins)
  • MPA|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

9.1 CSD87588N Package Dimensions

CSD87588N mechanical_drawing2_updated.png

Pin Configuration

Position Designation
Pin 1 TG
Pin 2 VIN
Pin 3 PGND
Pin 4 BG
Pin 5 VSW

9.2 Land Pattern Recommendation

CSD87588N Recommended_PCB_Pattern.png

9.3 Stencil Recommendation (100 µm)

CSD87588N Recommended_100um_Stencil2_Updated.png

9.4 Stencil Recommendation (125 µm)

CSD87588N Recommended_125um_Stencil2.png


For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques.

9.5 Pin Drawing

CSD87588N Pin_Drawing.png

9.6 CSD87588N Embossed Carrier Tape Dimensions

CSD87588N Tape_and_Reel.png
1. Pin 1 is oriented in the top-left quadrant of the tape enclosure (closest to the carrier tape sprocket holes).