SNAS621A JUNE   2013  – December 2014 DAC161S997

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Error Detection And Reporting
        1. 8.3.1.1 Loop Error
        2. 8.3.1.2 SPI Timeout Error (Channel Error)
        3. 8.3.1.3 Frame Error
        4. 8.3.1.4 Alarm Current
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface
        1. 8.4.1.1 SPI Write
        2. 8.4.1.2 SPI Read
        3. 8.4.1.3 Optional Protected SPI Writes
          1. 8.4.1.3.1 SPI Write Error Correction
    5. 8.5 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 16-bit Dac And Loop Drive
        1. 9.1.1.1 DC Characteristics
        2. 9.1.1.2 DC Input-Output Transfer Function
        3. 9.1.1.3 Loop Interface
        4. 9.1.1.4 Loop Compliance
        5. 9.1.1.5 AC Characteristics
          1. 9.1.1.5.1 Step Response
          2. 9.1.1.5.2 Output Impedance
          3. 9.1.1.5.3 PSRR
          4. 9.1.1.5.4 Stability
          5. 9.1.1.5.5 Noise and Ripple
          6. 9.1.1.5.6 Digital Feedthrough
          7. 9.1.1.5.7 HART Signal Injection
          8. 9.1.1.5.8 RC Filter Limitation
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Reasons for Choosing a 3.9-V Zener Diode
        2. 9.2.2.2 Loop Compliance Voltage
        3. 9.2.2.3 Selection of External BJT
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
Supply voltage (VA, VD to COMA, COMD) –0.3 6 V
Voltage between any two pins(2) 6 V
Current IN or OUT of any pin — except OUT pin(3) 5 mA
Output current at OUT 50 mA
Junction Temperature 150 °C
Operating Temperature –40 105 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to COMA = COMD = 0 V, unless otherwise specified.
(3) When the input voltage (VIN) at any pin exceeds power supplies (VIN < COMA or VIN > VA), the current at that pin must not exceed 5 mA, and the voltage (VIN) at that pin relative to any other pin must not exceed 6 V. See for Pin Descriptions for additional details of input structures.
(4) The Human Body Model (HBM) is a 100 pF capacitor charged to the specified voltage then discharged through a 1.5 kΩ resistor into each pin.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)(4) 2000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
BASE load to COMA 0 15 pF
(COMA - COMD) 0 V
OUT load to COMA none
(VA - VD) 0 V
VA, VDD Supply voltage 2.7 3.6 V
TA Temperature –40 105 °C

7.4 Thermal Information

DAC161S997 UNIT
WQFN
16 PINS
RθJA Package thermal impedance(1) 35 °C/W
(1) The package thermal impedance is calculated in accordance with JESD 51-7.

7.5 Electrical Characteristics

Unless otherwise noted, these specifications apply for VA = VD = 3.3 V, COMA = COMD = 0 V, TA= 25°C, external bipolar transistor: 2N3904, RE = 22 Ω, C1 = C2 = C3 = 2.2 nF.
PARAMETER TEST CONDITIONS MIN(7) TYP MAX(7) UNIT
POWER SUPPLY
VA, VD Supply voltage VA = VD
-40°C ≤ TA ≤ 105°C		 2.7 3.6 V
VA supply current DACCODE = 0x0200(1) 43 µA
VD supply current 57 µA
ICC Total supply current 100 125 µA
DC ACCURACY
N Resolution 16 bits
INL Integral non-linearity(6) 0x2AAA < DACCODE < 0xD555
(4 mA < ILOOP < 20 mA)		 –1.5 2.6 µA
DNL Differential non-linearity see (2) –0.2 0.2 µA
TUE Total unadjusted error 0x2AAA < DACCODE < 0xD555 0.01 %FS
OE Offset error see (3) –7.86 0.84 7.86 µA
ΔOE Offset error temperature coefficient -40°C ≤ TA ≤ 105°C 0.48 ppmFS/°C
GE Gain error see (4) 0.007 %FS
ΔGE Gain error temperature coefficient -40°C ≤ TA ≤ 105°C 5 ppmFS/°C
IERRL LOW ERROR current ERR_LOW = default 3.36 3.375 3.39 mA
IERRH HIGH ERROR current ERR_HIGH = default 21.70 21.75 21.82 mA
LTD Long term drift — mean shift of 12 mA output current after 1000 hours at 150°C 90 ppmFS
LOOP CURRENT OUTPUT (OUT)
IOUTMIN Minimum output current Tested at DACCODE = 0x01C2(5) 0.19 mA
IOUTMAX Maximum output current Tested at DACCODE = 0xFFFF 23.95 mA
ROUT Output impedance 200 MΩ
COMA to OUT voltage drop IOUT = 24 mA 960 mV
BASE OUTPUT
IOUTSC BASE short circuit output current BASE forced to COMA potential 10 mA
DYNAMIC CHARACTERISTICS
Output noise density 1 kHz 20 nA/rtHz
Integrated output noise 1 Hz to 1 kHz band 300 nARMS
INTERNAL TIMER
TM Timeout period Default setting of TIMEOUT in CONFIG register 100 ms
DIGITAL INPUT CHARACTERISTICS
IIN Digital input leakage current –10 10 µA
VIL Input low voltage 0.2 × VD V
VIH Input high voltage 0.7 × VD V
CIN Input capacitance 5 pF
DIGITAL OUTPUT CHARACTERISTICS
VOL Output Low voltage Isink = 200 μA 0.4 V
VOH Output HIGH voltage Isink = 200 μA 2.6 V
IOZH, IOZL TRI-STATE leakage current –10 10 µA
COUT TRI-STATE output capacitance 5 pF
(1) At code 0x0200 the BASE current is minimal, for example, device current contribution to power consumption is minimized. SPI is inactive, for example, after transmitting code 0x200 to the DAC161S997, there are no more transitions in the channel during the supply current measurement.
(2) Specified by design.
(3) Offset is the y-intercept of the straight line defined by 4 mA and 20 mA points of the measured transfer characteristic.
(4) Gain Error is the difference in slope of the straight line defined by measured 4 mA and 20 mA points of transfer characteristic, and that of the ideal characteristic.
(5) This must be treated as the minimum LOOP current ensured in self-powered mode.
(6) INL is measured using the best-fit method in the output current range of 4 mA to 20 mA.
(7) Limits are ensured by testing, design, or statistical analysis at 25°C. Limits over the operating temperature range are ensured through correlations using statistical quality control (SQC) method.

7.6 Timing Requirements

MIN NOM MAX UNIT
fCLK SCLK frequency 0 10 MHz
tH SCLK high time 0.4 / FCLK 50 ns
tL SCLK low time 0.4 / FCLK 50 ns
tCSB CSB pulse width 5 40 ns
tCSS CSB set-up time prior to SCLK rising edge 5 ns
tSCH 24th rising edge of SCLK to CSB rising edge 15 ns
tCSH CSB hold time after the 24th falling edge of SCLK 6 10 ns
tZSDO CSB falling edge to SDO valid 10 35 ns
tSDOZ CSB rising edge to SDO HiZ 10 ns
tDS SDI data set-up time prior to SCLK rising edge 10 ns
tDH SDI data hold time after SCLK rising edge 6 10 ns
tDO SDO output data valid 30 ns
DAC161S997 tim_1_snas621.gifFigure 1. SPI Timing Diagrams

7.7 Typical Characteristics

Unless otherwise noted, data presented here was collected under these conditions VA = VD = 3.3 V, TA = 25°C, external bipolar transistor: 2N3904, RE = 22 Ω, C1 = C2 = C3 = 2.2 nF.
DAC161S997 30154434.gif
Figure 2. Intergrated Noise vs ILOOP
DAC161S997 30154444.gif
Figure 4. Settling Time vs Input Step Size
DAC161S997 30154470.gif
Figure 6. PSRR: ILOOP = 4 mA
DAC161S997 30154442.gif
Figure 3. ΣΔ Modulator Filter Response
DAC161S997 30154469.gif
Figure 5. Output Linearity vs Temperature
DAC161S997 30154471.gif
Figure 7. PSRR: ILOOP = 20 mA