SLAS837B April   2013  – January 2017 DAC3174

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC Specifications
    6. 6.6 Electrical Characteristics: AC Specifications
    7. 6.7 Electrical Characteristics: Digital Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Alarm Monitoring
    4. 7.4 Device Functional Modes
      1. 7.4.1 Data Input Formats
      2. 7.4.2 Synchronization Modes
    5. 7.5 Programming
      1. 7.5.1 Initialization
      2. 7.5.2 Serial Interface Description
    6. 7.6 Register Maps
      1. 7.6.1  config0 Register (address = 0x00) [reset = 0x44FC]
      2. 7.6.2  config 1 Register (address = 0x01) [reset = 0x600E]
      3. 7.6.3  config2 Register (address = 0x02) [reset = 0x3FFF]
      4. 7.6.4  config3 Register (address = 0x03) [reset = 0x0000]
      5. 7.6.5  config4 Register (address = 0x04) [reset = 0x0000]
      6. 7.6.6  config5 Register (address = 0x05) [reset = 0x0000]
      7. 7.6.7  config6 Register (address = 0x06) [reset = 0x0000]
      8. 7.6.8  config7 Register (address = 0x07) [reset = 0xFFFF]
      9. 7.6.9  config8 Register (address = 0x08) [reset = 0x4000]
      10. 7.6.10 config9 Register (address = 0x09) [reset = 0x8000]
      11. 7.6.11 config10 Register (address = 0x0A) [reset = 0xF080]
      12. 7.6.12 config11 Register (address = 0x0B) [reset = 0x1111]
      13. 7.6.13 config12 Register (address = 0x0C) [reset = 0x3A7A]
      14. 7.6.14 config13 Register (address = 0x0D) [reset = 0x36B6]
      15. 7.6.15 config14 Register (address = 0x0E) [reset = 0x2AEA]
      16. 7.6.16 config15 Register (address = 0x0F) [reset = 0x0545]
      17. 7.6.17 config16 Register (address = 0x10) [reset = 0x0585]
      18. 7.6.18 config17 Register (address = 0x11) [reset = 0x0949]
      19. 7.6.19 config18 Register (address = 0x12) [reset = 0x1515]
      20. 7.6.20 config19 Register (address = 0x13) [reset = 0x3ABA]
      21. 7.6.21 config20 Register (address = 0x14) [reset = 0x0000]
      22. 7.6.22 config21 Register (address = 0x15) [reset = 0xFFFF]
      23. 7.6.23 config22 Register (address = 0x16) [reset = N/A]
      24. 7.6.24 config23 Register (address = 0x17) [reset = N/A]
      25. 7.6.25 config24 Register (address = 0x18) [reset = N/A]
      26. 7.6.26 config25 Register (address = 0x19) [reset = N/A]
      27. 7.6.27 config127 Register (address = 0x7F) [reset = 0x0045]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The DAC3174 device is a dual-channel, 14-bit, 500-MSPS, digital-to-analog converter (DAC), and uses a 14-bit, wide LVDS digital bus with an input FIFO. The data for the two channels are multiplexed onto the 14-bit LVDS bus in a dual-data-rate (DDR) fashion. The DAC3174 also supports a DDR, 7-bit, LVDS interface mode for each channel.

The DAC3174 has separate input data clock for the digital data and sample clock for the analog output. The FIFO input and output pointers can be synchronized across multiple devices for precise signal synchronization. The DAC outputs are current sourcing and terminate to GND with a compliance range of –0.5 V to +1 V. The DAC3174 is pin-compatible with the 12-bit DAC3164 and 10-bit DAC3154. as well as the single-channel DAC31x1 family.

7.2 Functional Block Diagrams

DAC3174 DAC3174.gif Figure 25. 14-Bit Interface Mode
DAC3174 DAC3174_7bit.gif Figure 26. 7-Bit Interface Mode

7.3 Feature Description

7.3.1 Alarm Monitoring

The DAC3174 includes flexible alarm monitoring that can be used to alert a possible malfunction scenario. All alarm events can be accessed either through the SIP registers and through the ALARM pin. After an alarm is set, the corresponding alarm bit in register config5 must be reset through the serial interface in order to allow further testing. The set of alarms includes the following conditions:

  • Zero check alarm
    • Alarm_from_zerochk: Occurs when the FIFO write pointer has an all zeros pattern. Because the write pointer is a shift register, all zeros cause the input point to be stuck until the next sync event. When this happens, a sync to the FIFO block is required.
  • FIFO alarms
    • alarm_from_fifo: Occurs when there is a collision in the FIFO pointers or a collision event is close.
    • alarm_fifo_2away: Pointers are within two addresses of each other.
    • alarm_fifo_1away: Pointers are within one address of each other.
    • alarm_fifo_collision: Pointers are equal to each other.
  • Clock alarms
    • clock_gone: Occurs when either the DACCLK or DATACLOCK have been stopped.
    • alarm_dacclk_gone: Occurs when the DACCLK has been stopped.
    • alarm_dataclk_gone: Occurs when the DATACLK has been stopped.
  • Pattern checker alarm
    • alarm_from_iotest: Occurs when the input data pattern does not match the pattern key.

To prevent unexpected DAC outputs from propagating into the transmit channel chain, the DAC3174 includes a feature that disables the outputs when a catastrophic alarm occurs. The catastrophic alarms include FIFO pointer collision, the loss DACCLK, or the loss of DATACLK. When any of these alarms occur, the internal TXenable signal is driven low and causes a zeroing of the data going to the DAC in < 10 T, where T = DACCLK period. One caveat is that if both clocks stop, the circuit cannot determine clock loss, so no alarms are generated; therefore, no zeroing of output data occurs.

7.4 Device Functional Modes

7.4.1 Data Input Formats

Table 1 through Table 4 list the single and dual bus clock modes of the DAC3174.

Table 1. Single Bus Single Clock Mode

DIFFERENTIAL PAIR (P/N) BITS
DATACLK RISING EDGE DATACLK FALLING EDGE
D13 A13 B13
D12 A12 B12
D11 A11 B11
D10 A10 B10
D9 A9 B9
D8 A8 B8
D7 A7 B7
D6 A6 B6
D5 A5 B5
D4 A4 B4
D3 A3 B3
D2 A2 B2
D1 A1 B1
D0 A0 B0
SYNC FIFO Write Reset —

Table 2. Single Channel SDR Mode

DIFFERENTIAL PAIR (P/N) BITS
DATACLK RISING EDGE DATACLK FALLING EDGE
D13 A13 —
D12 A12 —
D11 A11 —
D10 A10 —
D9 A9 —
D8 A8 —
D7 A7 —
D6 A6 —
D5 A5 —
D4 A4 —
D3 A3 —
D2 A2 —
D1 A1 —
D0 A0 —
SYNC FIFO Write Reset —

Table 3. Dual Bus Single Clock Mode

DIFFERENTIAL PAIR (P/N) DB_CLK RISING EDGE DB_CLK FALLING EDGE
DA6 A13 A6
DA5 A12 A5
DA4 A11 A4
DA3 A10 A3
DA2 A9 A2
DA1 A8 A1
DA0 A7 A0
DB6 B13 B6
DB5 B12 B5
DB4 B11 B4
DB3 B10 B3
DB2 B9 B2
DB1 B8 B1
DB0 B7 B0
SYNC FIFO Write Reset —

Table 4. Dual Bus Dual Clock Mode

DIFFERENTIAL PAIR (P/N) DA_CLK RISING EDGE DA_CLK FALLING EDGE
DA6 A13 A6
DA5 A12 A5
DA4 A11 A4
DA3 A10 A3
DA2 A9 A2
DA1 A8 A1
DA0 A7 A0
— DB_CLK RISING EDGE DB_CLK FALLING EDGE
DB6 B13 B6
DB5 B12 B5
DB4 B11 B4
DB3 B10 B3
DB2 B9 B2
DB1 B8 B1
DB0 B7 B0

NOTE

When rev (config0, bit 11) is asserted, the MSB through the LSB of the input bits are reversed. When using the 14-bit interface, all 14 bits are reversed as one word; when using the 7-bit interface, each of the 7 bits are reversed.

7.4.2 Synchronization Modes

There are three modes of syncing included in the DAC3174:

  • NORMAL Dual Sync—The SYNCx pin is used to align the input side of the FIFO (write pointers) with the A(0) sample. The ALIGNx pin is used to reset the output side of the FIFO (read pointers) to the offset value. Multiple chip alignment can be accomplished with this kind of syncing.
  • SYNC_ONLY—In this mode, only the SYNCx pin is used to sync both the read and write pointers of the FIFO. There is an asynchronous handoff between the DATACLK and DACCLK when using this mode; therefore, it is impossible to accurately align multiple chips closer than 2T or 3T, where T = DACCLK period.
  • SIF_SYNC— When neither SYNCx nor ALIGNx are used, a programmable synchronizing pulse is used to synchronize the design. However, the same issues for SYNC_ONLY mode apply. There is an asynchronous handoff between the serial clock domain and the two sides of the FIFO. Because of the asynchronous nature of SIF_SYNC method, it is impossible to align the sync with any sample at the input. SIF_SYNC mode is the only synchronization mode supported in dual-bus mode.

NOTE

When ALIGNP and ALIGNN are not used, TI recommends clearing alignrx_ena (config 1, bit 4), tying ALIGNP to DIGVDD18, and tying ALIGNN to ground. When SYNCP and SYNCN are not used, TI recommends clearing syncrx_ena (config 0, bit 3). Then, the unused SYNCP and SYNCN pins can be left open or tied to ground.

7.5 Programming

7.5.1 Initialization

The following startup sequence is recommended to power-up the DAC3174:

  1. Set TXENABLE low to prevent spurious output while initializing the device.
  2. Supply all 1.8-V voltages (VDDA18, DIGVDD18, CLKVDD18, and VFUSE) and all 3.3-V voltages (VDDA33, IOVDD, and PLLAVDD). Power IOVDD with a supply range of 1.8 V to 3.3 V. The 1.8-V and 3.3-V supplies can be powered up simultaneously, or in any order. There are no specific requirements on the ramp rate for the supplies.
  3. Provide all LVPECL inputs: DACCLKP, DACCLKN, and the optional ALIGNP and ALIGNN. These inputs can also be provided after the SIF register programming.
  4. Toggle the RESETB pin active low for a minimum pulse duration of 25 ns.
  5. Program the SIF registers.
  6. Make sure the FIFO pointers are properly initialized using one of the following methods:
    1. SYNCx and ALIGNx inputs
    2. SYNC-only input
    3. sif_sync programming with SYNC_only mode
  7. Set TXENABLE high.

7.5.2 Serial Interface Description

The serial port of the DAC3174 is a flexible serial interface that communicates with industry-standard microprocessors and microcontrollers. The interface provides read or write access to all registers used to define the operating modes of DAC3174. The interface is compatible with most synchronous transfer formats and can be configured as a 3- or 4-pin interface by sif4_ena (register config0, bit 9). In both configurations, SCLK is the serial interface input clock, and SDENB is serial interface enable. For 3-pin configuration, SDIO is a bidirectional pin for both data in and data out. For 4-pin configuration, SDIO is data in only, and SDO is data out only. Data are input into the device with the rising edge of SCLK. Data are output from the device on the falling edge of SCLK.

Each read or write operation is framed by signal SDENB (serial data enable bar) asserted low. The first frame byte is the instruction cycle that identifies the following data transfer cycle as read or write, as well as the 7-bit address to be accessed. Table 1 indicates the function of each bit in the instruction cycle, and is followed by a detailed description of each bit. The data transfer cycle consists of two bytes.

Table 1. Instruction Byte of the Serial Interface

MSB LSB
Bit 7 6 5 4 3 2 1 0
Description R/W A6 A5 A4 A3 A2 A1 A0
R/W Identifies the following data transfer cycle as a read or write operation. A high indicates a read operation from the DAC3174, and a low indicates a write operation to the DAC3174.
[A6:A0] Identifies the address of the register to be accessed during the read or write operation.

Figure 27 shows the serial interface timing diagram for a DAC3174 write operation. SCLK is the serial interface clock input to the DAC3174. Serial data enable SDENB is an active low input to the DAC3174. SDIO is serial data in. Input data to the DAC3174 is clocked on the rising edges of SCLK.

DAC3174 srl_if_wrt_dia_las837.gif Figure 27. Serial Interface Write Timing Diagram

Figure 28 shows the serial interface timing diagram for a DAC3174 read operation. SCLK is the serial interface clock input to the DAC3174. Serial data enable SDENB is an active low input to the DAC3174. SDIO is serial data in during the instruction cycle. In 3-pin configuration, SDIO is data out from the DAC3174 during the data transfer cycle, while SDO is in a high-impedance state. In 4-pin configuration, both SDIO and SDO are data out from the DAC3174 during the data transfer cycle. At the end of the data transfer, SDIO and SDO output low on the final falling edge of SCLK until the rising edge of SDENB when they become high impedance.

DAC3174 srl_if_rd_dia_las837.gif Figure 28. Serial Interface Read Timing Diagram

7.6 Register Maps

Table 5 lists the register maps for the DAC3174.

In the SIF interface, there are three types of registers:

  1. NORMAL
    • The NORMAL register type allows data to be written and read from. All 16-bits of the data are registered at the same time. There is no synchronizing with an internal clock thus all register writes are asynchronous with respect to internal clocks. There are three subtypes of NORMAL:
      • AUTOSYNC: A NORMAL register that causes a sync to be generated after the write is finished. These are most commonly used in things like offsets and phaseadd, where there is a word or block setup that extends across multiple registers, and all of the registers required to be programmed before any take effect on the circuit. For example, the phaseadd is two registers long. There is no benefit to have the first write 16 of the 32 bits cause a change in the frequency, so the design allows all the registers to be written. When the last register write for this block is finished, an autosync is generated for the mixer to read all the new SIF values. This occurs on a mixer clock cycle so that no metastability errors occur.
      • No RESET Value: These are NORMAL registers, but for one reason or another, the reset value can not be ensured. The reason may be because the register has some read-only bits, or some internal logic partially controls the bit values. An example is the SIF_CONFIG6 register. The bits come from the temperature sensor and the fuses. Depending on which fuses are blown and what the die temperature is, the reset value is different.
      • FUSE controlled: While not a type of register, fuses can affect what is read as the default value. The default values shown in this data sheet are for when no fuses are blown.
  2. READ_ONLY
    • Registers that are internal wires ANDed with the address bus, and then connected to the SIF output data bus.
  3. WRITE_TO_CLEAR:
    • These registers are just like NORMAL registers with one exception: these registers can be written and read. However, when the internal logic asynchronously sets a bit high in one of these registers, that bit stays high until written to 0. In this way, interrupts are captured and stay constant until cleared by the user.

Table 5. Register Map

NAME ADDR (HEX) DEFAULT BIT 15
(MSB)		 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(LSB)
config0 0x00 0x44FC qmc_ offset_ena dual_ ena chipwidth (1:0) rev twos sif4_ ena reserved fifo_ ena alarm_ out_ena alarm_ out_pol alignrx_ ena syncrx_ ena lvdsdataclk _ena reserved synconly_ena
config1 0x01 0x600E iotest_ena bsideclk_ ena fullword_ interface_ ena 64cnt_ ena dacclk_gone_ ena dataclkgone _ena collision_ ena reserved daca_ compliment dacb_ compliment sif_ sync sif_ sync_ena alarm_ 2away_ ena alarm_ 1away_ ena alarm _collision _ena reserved
config2 0x02 0x3FFF reserved lvdsdata_ena (13:0)
config3 0x03 0x0000 datadlya (2:0) clkdlya (2:0) datadlyb (2:0) clkdlyb (2:0) extref _ena reserved dual_ ena
config4 0x04 0x0000 reserved iotest_results (13:0)
config5 0x05 0x0000 alarm_ from_ zerochka alarm_ from_ zerochkb alarms_from_fifoa (2:0) alarms_from_fifob (2:0) alarm_ dacclk_ gone alarm_ dataclk_ gone clock_ gone alarm_ from_ iotesta alarm_ from_ iotestb reserved
config6 0x06 0x0000 tempdata (7:0) fuse_cntl (5:0) reserved
config7 0x07 0xFFFF alarms_mask (15:0)
config8 0x08 0x4000 reserved qmc_offseta (12:0)
config9 0x09 0x8000 fifo_offset (2:0) qmc_offsetb (12:0)
config10 0x0A 0xF080 coarse_dac (3:0) fuse_ sleep reserved reserved tsense_ sleep clkrecv_ ena sleepa sleepb reserved
config11 0x0B 0x1111 reserved reserved reserved reserved
config12 0x0C 0x3A7A reserved iotest_pattern0 (13:0)
config13 0x0D 0x36B6 reserved iotest_pattern1 (13:0)
config14 0x0E 0x2AEA reserved iotest_pattern2 (13:0)
config15 0x0F 0x0545 reserved iotest_pattern3 (13:0)
config16 0x10 0x0585 reserved iotest_pattern4 (13:0)
config17 0x11 0x0949 reserved iotest_pattern5 (13:0)
config18 0x12 0x1515 reserved iotest_pattern6 (13:0)
config19 0x13 0x3ABA reserved iotest_pattern7 (13:0)
config20 0x14 0x0000 sifdac_ ena reserved sifdac (13:0)
config21 0x15 0xFFFF sleepcntl (15:0)
config22 0x16 0x0000 fa002_data(15:0)
config23 0x17 0x0000 fa002_data(31:16)
config24 0x18 0x0000 fa002_data(47:32)
config25 0x19 0x0000 fa002_data(63:48)
config127 0x7F 0x0049 reserved reserved reserved reserved reserved titest_voh titest_vol vendorid (1:0) versionid (2:0)

7.6.1 config0 Register (address = 0x00) [reset = 0x44FC]

Figure 29. config0 Register
15 14 13 12 11 10 9 8
qmc_offset_ena dual_ena chipwidth1 chipwidth0 rev twos sif4_ena reserved
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0
7 6 5 4 3 2 1 0
fifo_ena alarm_out_ena alarm_out_pol alignrx_ena syncrx_ena lvdsdataclk_ena reserved synconly_ena
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. config0 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config0 0x00 15 qmc_offset_ena Enable the offset function when asserted. 0
14 dual_ena Uses both DACs when asserted. 1
(FUSE controlled)
13:12 chipwidth Programmable bits for setting the input interface width:
00: all 14 bits are used
01: upper 12 bits are used
10: upper 10 bits are used
11: upper 10 bits are used.		 00
11 rev Reverses the input bits. When using the 7-bit interface, this reverse each 7-bit input, however when using the 14-bit interface, all 14-bits are reversed as one word. 0
10 twos When asserted, this bit tells the chip to presume 2's complement data are arriving at the input. Otherwise offset binary is presumed. 1
9 sif4_ena When asserted the SIF interface becomes a 4-pin interface. This bit has a lower priority than the dieid_ena bit. 0
8 reserved Reserved 0
7 fifo_ena When asserted, the FIFO is absorbing the difference between INPUT clock and DAC clock. If it is not asserted then the FIFO buffering is bypassed but the reversing of bits and handling of offset binary input is still available. NOTE: When the FIFO is bypassed the DACCLK and DATACLK must be aligned or there may be timing errors; and, it is not recommended for actual application use. 1
6 alarm_out_ena When asserted the pin alarm becomes an output instead of a tri-state pin. 1
5 alarm_out_pol This bit changes the polarity of the ALARM signal (0 = negative logic, 1 = positive logic). 1
4 alignrx_ena When asserted the ALIGN pin receiver is powered up. NOTE: TI recommends clearing this bit when ALIGNP/N are not used (dual bus mode, and SYNC ONLY and SIF_SYNC modes in single bus mode). 1
3 syncrx_ena When asserted the SYNC pin receiver is powered up NOTE: TI recommends clearing this bit when SYNCP/N are not used (dual bus mode, and SIF_SYNC mode in single bus mode). 1
2 lvdsdataclk_ena When asserted the DATACLK pin receiver is powered up. 1
1 reserved Reserved 0
0 synconly_ena When asserted the chip is put into the SYNC ONLY mode where the SYNC ONLY pin is used as the sync input for both the front and back of the FIFO. 0

7.6.2 config 1 Register (address = 0x01) [reset = 0x600E]

Figure 30. config1 Register
15 14 13 12 11 10 9 8
iotest_ena bsideclk_ena fullwordinterface _ena 64cnt_ena dacclkgone_ ena dataclkgone_ ena collision_ena reserved
R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
daca_ compliment dacb_ compliment sif_sync sif_sync_ena alarm_2away_ ena alarm_1away_ ena alarm_collision_ena reserved
R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. config1 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config1 0x01 15 iotest_ena Turns on the io-testing circuitry when asserted. This is the circuitry that compares an 8-sample input pattern to SIF programmed registers to make sure the data coming into the chip meets setup and hold requirements. If this bit is a 0 then the clock to this circuitry is turned off for power savings. NOTE: Sample 0 must be aligned with the rising edge of SYNC. 0
14 bsideclk_ena When asserted the input clock for the B side datapath is enabled. Otherwise the IOTEST and the FIFO on the B-side of the design does not get a clock. 1
13 fullwordinterface_ena When asserted the input interface is changed to use the full 14-bits for each word, instead of dual, 7-bit buses for two half-words. 1
12 64cnt_ena This enables the resetting of the alarms after 64 good samples with the goal of removing unnecessary errors. For instance on a lab board, when checking the setup and hold through IOTEST, there may initially be errors, but once the test is up and running everything works. Setting this bit removes the requirement for a SIF write to clear the alarm register. 0
11 dacclkgone_ena This allows the DACCLK gone signal from the clock monitor to be used to shut the output off. 0
10 dataclkgone_ena This allows the DATACLK gone signal from the clock monitor to be used to shut the output off. 0
9 collision_ena This allows the collision alarm from the FIFO to shut the output off. 0
8 reserved Reserved 0
7 daca_compliment When asserted the output to the DACA is complimented. This allows the user of the chip to effectively change the + and – designations of the DAC output pins. 0
6 dacb_compliment When asserted the output to the DACB is complimented. This allows the user of the chip to effectively change the + and – designations of the DAC output pins. 0
5 sif_sync This is the SIF_SYNC signal. Whatever is programmed into this bit is used as the chip sync when SIF_SYNC mode is enabled.Design is sensitive to rising edges so programming from 0 → 1 is when the sync pulse is generated. 1 → 0 has no effect. 0
4 sif_sync_ena When asserted enable SIF_SYNC mode. 0
3 alarm_2away_ena When asserted, alarms from the FIFO that represent the pointers being 2 away are enabled. 1
2 alarm_1away_ena When asserted, alarms from the FIFO that represent the pointers being 1 away are enabled. 1
1 alarm_collision_ena When asserted, the collision of FIFO pointers causes an alarm to be generated. 1
0 reserved Reserved 0

7.6.3 config2 Register (address = 0x02) [reset = 0x3FFF]

Figure 31. config 2 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved lvdsdata_ena
R-0 R-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. config2 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config2 0x02 15 reserved Reserved 0
14 reserved Reserved 0
13:0 lvdsdata_ena These 14 bits are individual enables for the 14 input pin receivers: bits(13:7) turn on Da(6:0), where as bits(6:0) enable Db(6:0). 0x3FFF

7.6.4 config3 Register (address = 0x03) [reset = 0x0000]

Figure 32. config3 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
datadlya clkdlya datadlyb clkdlyb extref_ ena reserved dual_ clock_ena
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0
15 14 13 12 11 10 9 8
datadlya clkdlya datadlyb
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
datadlyb clkdlyb extref_ ena reserved dual_ clock_ena
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. config3 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config3 0x03 15:13 datadlya Controls the delay of the D[13:7]P/N inputs through the LVDS receivers for single bus mode; controls the delay of the DA[6:0]P/N inputs through the LVDS receivers for dual bus mode.
0 = no additional delay and each LSB adds a nominal 80 ps.		 000
12:10 clkdlya Controls the delay of the SYNCP/N inputs through the LVDS receivers for single bus mode; controls the delay of the DA_CLKP/N inputs through the LVDS receivers for dual bus mode.
0 = no additional delay and each LSB adds a nominal 80 ps.		 000
9:7 datadlyb Controls the delay of the D[6:0]P/N inputs through the LVDS receivers for single bus mode; controls the delay of the DB[6:0]P/N inputs through the LVDS receivers for dual bus mode.
0 = no additional delay and each LSB adds a nominal 80 ps.		 000
6:4 clkdlyb Controls the delay of the DATACLKP/N inputs through the LVDS receivers for single bus mode; controls the delay of the DB_CLKP/N inputs through the LVDS receivers for dual bus mode.
0 = no additional delay and each LSB adds a nominal 80 ps.		 000
3 extref_ ena Enables external reference for the DAC when set. 0
2:1 reserved Reserved 00
0 dual_ clock_ena When asserted it tells the LVDS input circuit that there are two individual data clocks. NOTE: Must be in SIF_SYNC mode. 0

7.6.5 config4 Register (address = 0x04) [reset = 0x0000]

Figure 33. config4 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved iotest_ results
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. config4 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config4
(WRITE TO CLEAR/No RESET Value)		 0x04 15:14 reserved Reserved 00
13:0 iotest_ results The values of these bits tell which bit in the input word failed during the io-test pattern comparison. [13:7] match up with the 7 bits from port A and [6:0] match up with bits from port B. 0x0000

7.6.6 config5 Register (address = 0x05) [reset = 0x0000]

Figure 34. config5 Register
15 14 13 12 11 10 9 8
alarm_from_ zerochka alarm_from_ zerochkb alarms_from_ fifoa alarms_from_ fifob
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
alarm_dacclk_ gone alarm_dataclk_ gone clock_gone alarm_from_ iotesta alarm_from_ iotestb reserved
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. config5 Register

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config5 (WRITE TO CLEAR) 0x05 15 alarm_from_ zerochka When this bit is asserted the FIFO A write pointer has an all zeros pattern in it. Because this pointer is a shift register, all zeros cause the input point to be stuck until the next sync. The result could be a repeated 8T pattern at the output if the mixer is off and no syncs occur. Check for this error tells the user that another sync is necessary to restart the FIFO write pointer. 0
14 alarm_from_ zerochkb When this bit is asserted the FIFO B write pointer has an all zeros pattern in it. Because this pointer is a shift register, all zeros cause the input point to be stuck until the next sync. The result could be a repeated 8T pattern at the output if the mixer is off and no syncs occur. Check for this error tells the user that another sync is necessary to restart the FIFO write pointer. 0
13:11 alarms_from_ fifoa These bits report the FIFO A pointer status:
000: all fine,
001: pointers are 2 away,
01x: pointers are 1 away,
1xx: FIFO pointer collision.		 000
10:8 alarms_from_ fifob These bits report the FIFO B pointer status:
000: all fine
001: pointers are 2 away
01x: pointers are 1 away
1xx: FIFO pointer collision		 0
7 alarm_dacclk_ gone Bit gets asserted when the DACCLK has been stopped long for enough cycles to be caught. The number of cycles varies with interpolation. 0
6 alarm_dataclk_ gone Bit gets asserted when the DATACLK has been stopped long for enough cycles to be caught. The number of cycles varies with interpolation. 0
5 clock_gone This bit gets set when either alarm_dacclk_gone or alarm_dataclk_gone are asserted. It controls the output of the CDRV_SER block. When high, the CDRV_SER block outputs 0x8000 for each output connected to a DAC. The bit must be written to 0 for CDRV_SER outputs to resume normal operation. 0
4 alarm_from_ iotesta This is asserted when the input data pattern does not match the pattern in the iotest_pattern registers. 0
3 alarm_from_ iotestb This is asserted when the input data pattern does not match the pattern in the iotest_pattern registers. 0
2 reserved Reserved 0
1 reserved Reserved 0
0 reserved Reserved 0

7.6.7 config6 Register (address = 0x06) [reset = 0x0000]

Figure 35. config6 Register
15 14 13 12 11 10 9 8
tempdata
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
fuse_cntl reserved
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. config6 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config6
(No RESET value)		 0x06 15:8 tempdata This the output from the chip temperature sensor.
NOTE: When reading these bits, the SIF interface must be extremely slow (1-MHz range).		 0x00
7:2 fuse_cntl These are the values of the blown fuses and are used to determine the available functionality in the chip.
NOTE: These bits are READ_ONLY and allow the user to check what features have been disabled in the device:
bit5 = 1: forces full word interface
bit4 = 1: reserved
bit3 = 1: reserved
bit2 = 1: forces single DAC mode. NOTE: This does not force the channel B in sleep mode. To do so, the user is required to program the sleepb SPI bit (config10, bit 5) to 1
bit1 = 0: Forces a different bits size;
00 = 14-bit
01 = 12-bit
10 = 10-bit
11 = 10-bit		 0x00
1 reserved Reserved 0
0 reserved Reserved 0

7.6.8 config7 Register (address = 0x07) [reset = 0xFFFF]

Figure 36. config7 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
alarms_ mask
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. config7 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config7 0x07 15:0 alarms_ mask Each bit is used to mask an alarm. Assertion masks the alarm:
bit15 = alarm_mask_zerochka
bit14 = alarm_mask_zerochkb
bit13 = alarm_mask_fifoa_collision
bit12 = alarm_mask_fifoa_1away
bit11 = alarm_mask_fifoa_2away
bit10 = alarm_mask_fifob_collision
bit9 = alarm_mask_fifob_1away
bit8 = alarm_mask_fifob_2away
bit7 = alarm_mask_dacclk_gone
bit6 = alarm_mask_dataclk_gone
bit5 = masks the signal which turns off the DAC output when a clock or collision occurs (this bit has no effect on the PAD_ALARM output),
bit4 = alarm_mask_iotesta
bit3 = alarm_mask_iotestb
bit2 = reserved
bit1 = reserved
bit0 = reserved		 0xFFFF

7.6.9 config8 Register (address = 0x08) [reset = 0x4000]

Figure 37. config8 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved qmc_ offseta
R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. config8 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config8 0x08 15:13 reserved Reserved 010
12:0 qmc_ offseta The DAC A offset correction. The offset is measured in DAC LSBs. 0x0000

7.6.10 config9 Register (address = 0x09) [reset = 0x8000]

Figure 38. config9 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
fifo_ offset qmc_ offsetb
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. config9 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config9
(AUTO SYNC)		 0x09 15:13 fifo_ offset This is the starting point for the READ_POINTER in the FIFO block. The READ_POINTER is set to this location when a sync occurs on the DACCLK side of the FIFO. 100
12:0 qmc_ offsetb The DAC B offset correction. The offset is measured in DAC LSBs. NOTE: Writing this register causes an autosync to be generated in the QMOFFSET block. 0x0000

7.6.11 config10 Register (address = 0x0A) [reset = 0xF080]

Figure 39. config10 Register
15 14 13 12 11 10 9 8
coarse_ dac fuse_ sleep reserved reserved tsense_ sleep
R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0
7 6 5 4 3 2 1 0
clkrecv_ ena sleepa sleepb reserved
R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. config10 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config10 0x0A 15:12 coarse_ dac Scales the output current in 16 equal steps. 1111
DAC3174 EQ1_vref_las837.gif
11 fuse_ sleep Put the fuses to sleep when set high. 0
10 reserved Reserved 0
9 reserved Reserved 0
8 tsense_ sleep When asserted the temperature sensor is put to sleep. 0
7 clkrecv_ ena Turn on the DAC CLOCK receiver block when asserted. 1
6 sleepa When asserted DACA is put to sleep. 0
5 sleepb When asserted DACB is put to sleep. NOTE: This bit is required to be programmed to 1 for single DAC mode. 0
4:0 reserved Reserved 00000

7.6.12 config11 Register (address = 0x0B) [reset = 0x1111]

Figure 40. config11 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved reserved reserved reserved
R-0 R-0 R-0 R-1 R-0 R-0 R-0 R-1 R-0 R-0 R-0 R-1 R-0 R-0 R-0 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. config11 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config11 0x0B 15:12 reserved Reserved 0001
11:8 reserved Reserved 0001
7:4 reserved Reserved 0001
3:0 reserved Reserved 0001

7.6.13 config12 Register (address = 0x0C) [reset = 0x3A7A]

Figure 41. config12 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved iotest_ pattern0
R-0 R-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. config12 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config12 0x0C 15:14 reserved Reserved 00
13:0 iotest_ pattern0 This is dataword0 in the IO test pattern. It is used with the seven other words to test the input data. NOTE: This word must be aligned with the rising edge of SYNC when testing the IO interface. 0x3A7A

7.6.14 config13 Register (address = 0x0D) [reset = 0x36B6]

Figure 42. config13 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved iotest_ pattern1
R-0 R-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. config13 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config13 0x0D 15:14 reserved Reserved 00
13:0 iotest_ pattern1 This is dataword1 in the IO test pattern. It is used with the seven other words to test the input data. 0x36B6

7.6.15 config14 Register (address = 0x0E) [reset = 0x2AEA]

Figure 43. config14 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved iotest_ pattern2
R-0 R-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. config14 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config14 0x0E 15:14 reserved Reserved 00
13:0 iotest_ pattern2 This is dataword2 in the IO test pattern. It is used with the seven other words to test the input data. 0x2AEA

7.6.16 config15 Register (address = 0x0F) [reset = 0x0545]

Figure 44. config15 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved iotest_ pattern3
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. config15 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config15 0x0F 15:14 reserved Reserved 00
13:0 iotest_ pattern3 This is dataword3 in the IO test pattern. It is used with the seven other words to test the input data. 0x0545

7.6.17 config16 Register (address = 0x10) [reset = 0x0585]

Figure 45. config16 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved iotest_ pattern4
R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. config16 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config16 0x10 15:14 reserved Reserved 00
13:0 iotest_ pattern4 This is dataword4 in the IO test pattern. It is used with the seven other words to test the input data. 0x0585

7.6.18 config17 Register (address = 0x11) [reset = 0x0949]

Figure 46. config17 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved iotest_ pattern5
R-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. config17 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config17 0x11 15:14 reserved Reserved 00
13:0 iotest_ pattern5 This is dataword5 in the IO test pattern. It is used with the seven other words to test the input data. 0x0949

7.6.19 config18 Register (address = 0x12) [reset = 0x1515]

Figure 47. config18 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved iotest_ pattern6
R-0 R-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. config18 Register Field Description

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config18 0x12 15:14 reserved Reserved 00
13:0 iotest_ pattern6 This is dataword6 in the IO test pattern. It is used with the seven other words to test the input data. 0x1515

7.6.20 config19 Register (address = 0x13) [reset = 0x3ABA]

Figure 48. config19 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
reserved iotest_ pattern7
R-0 R-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. config19 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config19 0x13 15:14 reserved Reserved 00
13:0 iotest_ pattern7 This is dataword7 in the IO test pattern. It is used with the seven other words to test the input data. 0x3ABA

7.6.21 config20 Register (address = 0x14) [reset = 0x0000]

Figure 49. config20 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sifdac_ ena reserved sifdac
R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 26. config20 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config20 0x14 15 sifdac_ ena When asserted the DAC output is set to the value in sifdac. This can be used for trim setting and other static tests. 0
14 reserved Reserved 0
13:0 sifdac This is the value that is sent to the DACs when sifdac_ena is asserted. 0x0000

7.6.22 config21 Register (address = 0x15) [reset = 0xFFFF]

Figure 50. config21 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
sleepcntl
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 27. config21 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config21 0x15 15:0 sleepcntl This controls what blocks is sent a SLEEP signal when the PAD_SLEEP pin is asserted. Programming a 1 in a bit passes the SLEEP signal to the appropriate block:
bit15 = DAC A
bit14 = DAC B
bit13 = FUSE sleep
bit12 = temperature sensor
bit11 = clock receiver
bit10 = LVDS DATA receivers
bit9 = LVDS SYNC receiver
bit8 = PECL ALIGN receiver
bit7 = LVDS DATACLK receiver
bit6 = reserved
bit5 = reserved
bit4 = reserved
bit3 = reserved
bit2 = reserved
bit1 = reserved
bit0 = reserved		 0xFFFF

7.6.23 config22 Register (address = 0x16) [reset = N/A]

Figure 51. config22 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
fa002_ data(15:0)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 28. config22 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config22
(READ ONLY)		 0x16 15:0 fa002_ data(15:0) Lower 16 bits of the DIE ID word N/A

7.6.24 config23 Register (address = 0x17) [reset = N/A]

Figure 52. config23 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
fa002_ data(31:16)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 29. config23 Register Field Description

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config23
(READ ONLY)		 0x17 15:0 fa002_ data(31:16) Lower-middle 16 bits of the DIE ID word N/A

7.6.25 config24 Register (address = 0x18) [reset = N/A]

Figure 53. config24 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
fa002_ data(47:32)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 30. config24 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config24
(READ ONLY)		 0x18 15:0 fa002_ data(47:32) Upper-middle 16 bits of the DIE ID word N/A

7.6.26 config25 Register (address = 0x19) [reset = N/A]

Figure 54. config25 Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
fa002_ data(63:48)
N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 31. config25 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config25
(READ ONLY)		 0x19 15:0 fa002_ data(63:48) Upper 16 bits of the DIE ID word N/A

7.6.27 config127 Register (address = 0x7F) [reset = 0x0045]

Figure 55. config127 Register
15 14 13 12 11 10 9 8
reserved reserved reserved reserved
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7 6 5 4 3 2 1 0
reserved titest_voh titest_vol vendorid versionid
R-0 R-1 R-0 R-0 R-1 R-0 R-0 R-1
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 32. config127 Register Field Descriptions

REG NAME ADDR (HEX) BIT NAME FUNCTION DEFAULT VALUE
config127
(READ ONLY and no RESET value)		 0x7F 15:14 reserved Reserved 00
13:12 reserved Reserved 00
11:10 reserved Reserved 00
9:8 reserved Reserved 00
7 reserved Reserved 0
6 titest_voh A fixed 1 that can be used to test the VOH at the SIF output 1
5 titest_vol A fixed 0 that can be used to test the VOL at the SIF output 0
4:3 vendorid Fixed at 01 01
2:0 versionid Chip version 001