SLAS837B April   2013  – January 2017 DAC3174

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: DC Specifications
    6. 6.6 Electrical Characteristics: AC Specifications
    7. 6.7 Electrical Characteristics: Digital Specifications
    8. 6.8 Timing Requirements
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Alarm Monitoring
    4. 7.4 Device Functional Modes
      1. 7.4.1 Data Input Formats
      2. 7.4.2 Synchronization Modes
    5. 7.5 Programming
      1. 7.5.1 Initialization
      2. 7.5.2 Serial Interface Description
    6. 7.6 Register Maps
      1. 7.6.1  config0 Register (address = 0x00) [reset = 0x44FC]
      2. 7.6.2  config 1 Register (address = 0x01) [reset = 0x600E]
      3. 7.6.3  config2 Register (address = 0x02) [reset = 0x3FFF]
      4. 7.6.4  config3 Register (address = 0x03) [reset = 0x0000]
      5. 7.6.5  config4 Register (address = 0x04) [reset = 0x0000]
      6. 7.6.6  config5 Register (address = 0x05) [reset = 0x0000]
      7. 7.6.7  config6 Register (address = 0x06) [reset = 0x0000]
      8. 7.6.8  config7 Register (address = 0x07) [reset = 0xFFFF]
      9. 7.6.9  config8 Register (address = 0x08) [reset = 0x4000]
      10. 7.6.10 config9 Register (address = 0x09) [reset = 0x8000]
      11. 7.6.11 config10 Register (address = 0x0A) [reset = 0xF080]
      12. 7.6.12 config11 Register (address = 0x0B) [reset = 0x1111]
      13. 7.6.13 config12 Register (address = 0x0C) [reset = 0x3A7A]
      14. 7.6.14 config13 Register (address = 0x0D) [reset = 0x36B6]
      15. 7.6.15 config14 Register (address = 0x0E) [reset = 0x2AEA]
      16. 7.6.16 config15 Register (address = 0x0F) [reset = 0x0545]
      17. 7.6.17 config16 Register (address = 0x10) [reset = 0x0585]
      18. 7.6.18 config17 Register (address = 0x11) [reset = 0x0949]
      19. 7.6.19 config18 Register (address = 0x12) [reset = 0x1515]
      20. 7.6.20 config19 Register (address = 0x13) [reset = 0x3ABA]
      21. 7.6.21 config20 Register (address = 0x14) [reset = 0x0000]
      22. 7.6.22 config21 Register (address = 0x15) [reset = 0xFFFF]
      23. 7.6.23 config22 Register (address = 0x16) [reset = N/A]
      24. 7.6.24 config23 Register (address = 0x17) [reset = N/A]
      25. 7.6.25 config24 Register (address = 0x18) [reset = N/A]
      26. 7.6.26 config25 Register (address = 0x19) [reset = N/A]
      27. 7.6.27 config127 Register (address = 0x7F) [reset = 0x0045]
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RGC Package
64-Pin VQFN
Top View

Pin Functions: Single-Bus Mode

PIN I/O DESCRIPTION
NAME NO.
CONTROL AND SERIAL
ALARM 47 O CMOS output for ALARM condition.
RESETB 41 I Serial interface reset input, active low. Initialized internal registers during high-to-low transition. Asynchronous. Internal pullup. A reset event after every power cycle may be required to reinitialize all SPI registers to default values.
SCLK 43 I Serial interface clock. Internal pulldown.
SDENB 42 I Serial data enable. Internal pullup.
SDIO 44 I/O Bidirectional serial data in 3-pin mode (default). In 4-pin interface mode (sif4_ena [config0, bit 9]), the SDIO pin in an input only. Internal pulldown.
SDO 46 O Unidirectional serial interface data in 4-pin mode (sif4_ena [config0, bit 9]). The SDO pin is made high impedance in 3-pin interface mode (default). Internal pulldown.
SLEEP 49 I Puts device in sleep, active high. Internal pulldown.
TXENABLE 48 I Transmit enable, active high input. TXENABLE must be high for the data to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data are ignored. Internal pulldown.
DATA INTERFACE
ALIGNN 5 I LVPECL FIFO output synchronization. This positive or negative pair is captured with the rising edge of DACCLKx. This pin is used to reset the clock dividers and for multiple DAC synchronization. If unused, this pin can be left unconnected.
ALIGNP 4 I
DATA[13:0]N 10, 12, 14, 16, 18, 20, 23, 27, 30, 32, 34, 36, 38, 40 I LVDS input data bits for both channels. Each positive and negative LVDS pair has an internal 100-Ω termination resistor. Data format relative to DATACLKx clock is dual data rate (DDR) with two data transfers per DATACLKx clock cycles.

The data format is interleaved with channel A (rising edge) and channel B (falling edge).


In the default mode (reverse bus not enabled):


DATA13x is most significant data bit (MSB)


DATA0x is least significant data bit (LSB)
DATA[13:0]P 9, 11, 13, 15, 17, 19, 22, 26, 29, 31, 33, 35, 37, 39 I
DATACLKN 25 I DDR differential input data clock. Edge to center nominal timing. Ch A rising edge, Ch B falling edge in multiplexed output mode.
DATACLKP 24 I
SYNCN 7 I This pin resets the FIFO or is used as a syncing source. These two functions are captured with the rising edge of DATACLKx. The signal captured by the falling edge of DATACLKx.
SYNCP 6 I
OUTPUT AND CLOCK
DACCLKN 2 I LVPECL clock input for DAC core with a self-bias of approximately CLKVDD18 / 2.
DACCLKP 1 I
IOUTAN 60 O A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale current source, and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input results in a 0-mA current source, and the least positive voltage on the IOUTAP pin. The IOUTAN pin is the complement of IOUTAP.
IOUTAP 61 O
IOUTBN 54 O B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale current source, and the most positive voltage on the IOUTBP pin. Similarly, a 0xFFFF data input results in a 0-mA current source, and the least positive voltage on the IOUTBP pin. The IOUTBN pin is the complement of IOUTBP.
IOUTBP 53 O
REFERENCE
BIASJ 57 O Full-scale output current bias. For 20-mA full-scale output current, connect a 960-Ω resistor to GND.
EXTIO 58 I/O Used as external reference input when internal reference is disabled. Requires a 0.1-µF decoupling capacitor to GND when used as reference output.
POWER SUPPLY
CLKVDD18 3 I 1.8-V clock supply.
DIGVDD18 21, 28 I 1.8-V digital supply. Also supplies LVDS receivers.
IOVDD 45 I Supply voltage for CMOS I/Os. 1.8 V to 3.3 V.
VDDA18 50, 64 I Analog 1.8-V supply.
VDDA33 55, 56, 59 I Analog 3.3-V supply.
VFUSE 8 I Digital supply voltage (1.8 V). This supply pin is also used for factory fuse programming. Connect to DVDD pins for normal operation.
NC 51, 52,
62, 63		 — Not used. These pins can be left open or tied to ground in actual application use.
GND PAD — — This thermal pad is the electrical ground connection for the device (backside).
RGC Package
64-Pin VQFN
Top View

Pin Functions: Dual-Bus Mode

PIN I/O DESCRIPTION
NAME NO.
CONTROL AND SERIAL
ALARM 47 O CMOS output for alarm condition.
RESETB 41 I Serial interface reset input, active low. Initializes internal registers during high to low transition. Asynchronous. Internal pullup. A reset event after every power cycle may be required to reinitialize all SPI registers to default values.
SCLK 43 I Serial interface clock. Internal pulldown.
SDENB 42 I Serial data enable. Internal pullup.
SDIO 44 I/O Bidirectional serial data in 3-pin mode (default). In 4-pin interface mode (sif4_ena [config0, bit 9]), the SDIO pin in an input only. Internal pulldown.
SDO 46 O Unidirectional serial interface data in 4-pin mode (sif4_ena [config0, bit 9]). The SDO pin is made high impedance in 3-pin interface mode (default). Internal pulldown.
SLEEP 49 I Puts device in sleep, active high. Internal pulldown.
TXENABLE 48 I Transmit enable, active high input. TXENABLE must be high for the data to the DAC to be enabled. When TXENABLE is low, the digital logic section is forced to all 0, and any input data are ignored. Internal pulldown.
DATA INTERFACE
DA[6:0]N 10, 12, 14, 16, 18 I LVDS positive input data bits for channel A. Each positive or negative LVDS pair has an internal 100-Ω termination resistor. Data format relative to DA_CLKx clock is dual data rate (DDR) with two data transfers per DA_CLKx clock cycle.
The data format is 7 MSBs (rising edge) and 7 LSBs (falling edge).
In the default mode (reverse bus not enabled):
DA6x is most significant data bit (MSB)
DA0x is least significant data bit (LSB)
DA[6:0]P 9, 11, 13, 15, 17, 19 I
DB[6:0]N 27, 30, 32, 34, 36, 38, 40 I LVDS positive input data bits for channel B. Each positive or negative LVDS pair has an internal 100-Ω termination resistor. Data format relative to DB_CLKx clock is dual data rate (DDR) with two data transfers per DB_CLKx clock cycle.
The data format is 7 MSBs (rising edge) and 7 LSBs (falling edge).
In the default mode (reverse bus not enabled):
DB6x is most significant data bit (MSB)
DB0x is least significant data bit (LSB)
DB[6:0]P 26, 29, 31, 33, 35, 37, 39 I
DA_CLKN 7 I DDR differential input data clock for channel A. Edge to center nominal timing.
DA_CLKP 6 I
DB_CLKN 25 I DDR differential input data clock for channel B. Edge to center nominal timing.
DB_CLKP 24 I
OUTPUT AND CLOCK
DACCLKN 2 I LVPECL clock negative input for DAC core with a self-bias of approximately CLKVDD18 / 2.
DACCLKP 1 I LVPECL clock positive input for DAC core with a self-bias of approximately CLKVDD18 / 2.
IOUTAN 60 O A-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale current source, and the most positive voltage on the IOUTAP pin. Similarly, a 0xFFFF data input results in a 0-mA current source, and the least positive voltage on the IOUTAP pin. The IOUTAN pin is the complement of IOUTAP.
IOUTAP 61 O
IOUTBN 54 O B-Channel DAC current output. An offset binary data pattern of 0x0000 at the DAC input results in a full-scale current source, and the most positive voltage on the IOUTBP pin. Similarly, a 0xFFFF data input results in a 0-mA current source, and the least positive voltage on the IOUTBP pin. The IOUTBN pin is the complement of IOUTBP.
IOUTBP 53 O
REFERENCE
BIASJ 57 O Full-scale output current bias. For 20-mA full-scale output current, connect a 960-Ω resistor to GND.
EXTIO 58 I/O Used as external reference input when internal reference is disabled. Requires a 0.1-µF decoupling capacitor to GND when used as reference output.
POWER SUPPLY
CLKVDD18 3 I 1.8-V clock supply.
DIGVDD18 21, 28 I 1.8-V digital supply. Also supplies LVDS receivers.
IOVDD 45 I Supply voltage for CMOS I/Os. 1.8 V to 3.3 V.
VDDA18 50, 64 I Analog 1.8-V supply.
VDDA33 55, 56, 59 I Analog 3.3-V supply.
VFUSE 8 I Digital supply voltage (1.8 V). This supply pin is also used for factory fuse programming. Connect to DVDD pins for normal operation.
NC 4, 5,
51, 52,
62, 63		 — Not used. In actual application, pins 51, 52, 62, and 63 can be left open or tied to ground. TI recommends tying pins 4 and 5 to DIGVDD18 and ground, respectively.
GND PAD — — This thermal pad is the electrical ground connection for the device (backside).