SLASEA3C December   2016  – July 2017 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics - DC Specifications
    6. 7.6  Electrical Characteristics - Digital Specifications
    7. 7.7  Electrical Characteristics - AC Specifications
    8. 7.8  PLL/VCO Electrical Characteristics
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1  SerDes Inputs
      2. 8.3.2  SerDes Rate
      3. 8.3.3  SerDes PLL
      4. 8.3.4  SerDes Equalizer
      5. 8.3.5  JESD204B Descrambler
      6. 8.3.6  JESD204B Frame Assembly
      7. 8.3.7  SYNC Interface
      8. 8.3.8  Single or Dual Link Configuration
      9. 8.3.9  Multi-Device Synchronization
      10. 8.3.10 SYSREF Capture Circuit
      11. 8.3.11 JESD204B Subclass 0 support
      12. 8.3.12 SerDes Test Modes through Serial Programming
      13. 8.3.13 SerDes Test Modes through IEEE 1500 Programming
      14. 8.3.14 Error Counter
      15. 8.3.15 Eye Scan
      16. 8.3.16 JESD204B Pattern Test
      17. 8.3.17 Multiband DUC (multi-DUC)
        1. 8.3.17.1 Multi-DUC input
        2. 8.3.17.2 Interpolation Filters
        3. 8.3.17.3 JESD204B Modes, Interpolation and Clock phase Programming
        4. 8.3.17.4 Digital Quadrature Modulator
        5. 8.3.17.5 Low Power Coarse Resolution Mixing Modes
        6. 8.3.17.6 Inverse Sinc Filter
        7. 8.3.17.7 Summation Block for Dual DUC Modes
      18. 8.3.18 PA Protection Block
      19. 8.3.19 Gain Block
      20. 8.3.20 Output Summation
      21. 8.3.21 Output Delay
      22. 8.3.22 Polarity Inversion
      23. 8.3.23 Temperature Sensor
      24. 8.3.24 Alarm Monitoring
      25. 8.3.25 Differential Clock Inputs
      26. 8.3.26 CMOS Digital Inputs
      27. 8.3.27 DAC Fullscale Output Current
      28. 8.3.28 Current Steering DAC Architecture
      29. 8.3.29 DAC Transfer Function for DAC38RF83, 93, 85
      30. 8.3.30 DAC Transfer Function for DAC38RF80/90/84
    4. 8.4 Device Functional Modes
      1. 8.4.1 Clocking Modes
      2. 8.4.2 PLL Bypass Mode Programming
      3. 8.4.3 Internal PLL/VCO
      4. 8.4.4 CLKOUT
      5. 8.4.5 Serial Peripheral Interface (SPI)
        1. 8.4.5.1 NORMAL (RW)
        2. 8.4.5.2 WRITE_TO_CLEAR (W0C)
    5. 8.5 Register Maps
      1. 8.5.1  Chip Reset and Configuration Register (address = 0x00) [reset = 0x5803]
      2. 8.5.2  IO Configuration Register (address = 0x01) [reset = 0x1800]
      3. 8.5.3  Lane Single Detect Alarm Mask Register (address = 0x02) [reset = 0xFFFF]
      4. 8.5.4  Clock Alarms Mask Register (address = 0x03) [reset = 0xFFFF
      5. 8.5.5  SERDES Loss of Signal Detection Alarms Register (address = 0x04) [reset = 0x0000]
      6. 8.5.6  SYSREF Alignment Circuit Alarms Register (address = 0x05) [reset = 0x0000]
      7. 8.5.7  Temperature Sensor and PLL Loop Voltage Register (address = 0x06) [reset = variable]
      8. 8.5.8  Page Set Register (address = 0x09) [reset = 0x0000]
      9. 8.5.9  SYSREF Align to r1 and r3 Count Register (address = 0x78) [reset = 0x0000]
      10. 8.5.10 SYSREF Phase Count 1 and 2 Register (address = 0x79) [reset = 0x0000]
      11. 8.5.11 SYSREF Phase Count 3 and 4 Register (address = 0x7A) [reset = 0x0000]
      12. 8.5.12 Vendor ID and Chip Version Register (address = 0x7F) [reset = 0x0008]]
      13. 8.5.13 Multi-DUC Configuration (PAP, Interpolation) Register (address = 0x0A) [reset = 0x02B0]
      14. 8.5.14 Multi-DUC Configuration (Mixers) Register (address = 0x0C) [reset = 0x2402]
      15. 8.5.15 JESD FIFO Control Register (address = 0x0D) [reset = 0x1300]
      16. 8.5.16 Alarm Mask 1 Register (address = 0x0E) [reset = 0x00FF]
      17. 8.5.17 Alarm Mask 2 Register (address = 0x0F) [reset = 0xFFFF]
      18. 8.5.18 Alarm Mask 3 Register (address = 0x10) [reset = 0xFFFF]
      19. 8.5.19 Alarm Mask 4 Register (address = 0x11) [reset = 0xFFFF]
      20. 8.5.20 JESD Lane Skew Register (address = 0x12) [reset = 0x0000]
      21. 8.5.21 CMIX Configuration Register (address = 0x17) [reset = 0x0000]
      22. 8.5.22 Output Summation and Delay Register (address = 0x19) [reset = 0x0000]
      23. 8.5.23 NCO Phase Path AB Register (address = 0x1C) [reset = 0x0000]
      24. 8.5.24 NCO Phase Path CD Register (address = 0x1D) [reset = 0x0000]
      25. 8.5.25 NCO Frequency Path AB Register (address = 0x1E-0x20) [reset = 0x0000 0000 0000]
      26. 8.5.26 NCO Frequency Path CD Register (address = 0x21-0x23) [reset = 0x0000 0000 0000]
      27. 8.5.27 SYSREF Use for Clock Divider Register (address = 0x24) [reset = 0x0010]
      28. 8.5.28 Serdes Clock Control Register (address = 0x25) [reset = 0x7700]
      29. 8.5.29 Sync Source Control 1 Register (address = 0x27) [reset = 0x1144]
      30. 8.5.30 Sync Source Control 2 Register (address = 0x28) [reset = 0x0000]
      31. 8.5.31 PAP path AB Gain Attenuation Step Register (address = 0x29) [reset = 0x0000]
      32. 8.5.32 PAP path AB Wait Time Register (address = 0x2A) [reset = 0x0000]
      33. 8.5.33 PAP path CD Gain Attenuation Step Register (address = 0x2B) [reset = 0x0000]
      34. 8.5.34 PAP Path CD Wait Time Register (address = 0x2C) [reset = 0x0000]
      35. 8.5.35 PAP path AB Configuration Register (address = 0x2D) [reset = 0x0FFF]
      36. 8.5.36 PAP path CD Configuration Register (address = 0x2E) [reset = 0x0FFF]
      37. 8.5.37 DAC SPI Configuration Register (address = 0x2F) [reset = 0x0000]
      38. 8.5.38 DAC SPI Constant Register (address = 0x30) [reset = 0x0000]
      39. 8.5.39 Gain for path AB Register (address = 0x32) [reset = 0x0000]
      40. 8.5.40 Gain for path CD Register (address = 0x33) [reset = 0x0000]
      41. 8.5.41 JESD Error Counter Register (address = 0x41) [reset = 0x0000]
      42. 8.5.42 JESD ID 1 Register (address = 0x46) [reset = 0x0044]
      43. 8.5.43 JESD ID 2 Register (address = 0x47) [reset = 0x190A]
      44. 8.5.44 JESD ID 3 and Subclass Register (address = 0x48) [reset = 0x31C3]
      45. 8.5.45 JESD Lane Enable Register (address = 0x4A) [reset = 0x0003]
      46. 8.5.46 JESD RBD Buffer and Frame Octets Register (address = 0x4B) [reset = 0x1300]
      47. 8.5.47 JESD K and L Parameters Register (address = 0x4C) [reset = 0x1303]
      48. 8.5.48 JESD M and S Parameters Register (address = 0x4D) [reset = 0x0100]
      49. 8.5.49 JESD N, HD and SCR Parameters Register (address = 0x4E) [reset = 0x0F4F]
      50. 8.5.50 JESD Character Match and Other Register (address = 0x4F) [reset = 0x1CC1]
      51. 8.5.51 JESD Link Configuration Data Register (address = 0x50) [reset = 0x0000]
      52. 8.5.52 JESD Sync Request Register (address = 0x51) [reset = 0x00FF]
      53. 8.5.53 JESD Error Output Register (address = 0x52) [reset = 0x00FF]
      54. 8.5.54 JESD ILA Check 1 Register (address = 0x53) [reset = 0x0100]
      55. 8.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
      56. 8.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
      57. 8.5.57 JESD Crossbar Configuration 1 Register (address = 0x5F) [reset = 0x0123]
      58. 8.5.58 JESD Crossbar Configuration 2 Register (address = 0x60) [reset = 0x4567]
      59. 8.5.59 JESD Alarms for Lane 0 Register (address = 0x64) [reset = 0x0000]
      60. 8.5.60 JESD Alarms for Lane 1 Register (address = 0x65 01100101) [reset = 0x0000]
      61. 8.5.61 JESD Alarms for Lane 2 Register (address = 0x66) [reset = 0x0000]
      62. 8.5.62 JESD Alarms for Lane 3 Register (address = 0x67) [reset = 0x0000]
      63. 8.5.63 JESD Alarms for Lane 4 Register (address = 0x68) [reset = 0x0000]
      64. 8.5.64 JESD Alarms for Lane 5 Register (address = 0x69) [reset = 0x0000]
      65. 8.5.65 JESD Alarms for Lane 6 Register (address = 0x6A [reset = 0x0000]
      66. 8.5.66 JESD Alarms for Lane 7 Register (address = 0x6B) [reset = 0x0000]
      67. 8.5.67 SYSREF and PAP Alarms Register (address = 0x6C) [reset = 0x0000]
      68. 8.5.68 Clock Divider Alarms 1 Register (address = 0x6D) [reset = 0x0000]
      69. 8.5.69 Clock Configuration Register (address = 0x0A) [reset = 0xF000]
      70. 8.5.70 Sleep Configuration Register (address = 0x0B) [reset = 0x0022]
      71. 8.5.71 Divided Output Clock Configuration Register (address = 0x0C) [reset = 0x8000]
      72. 8.5.72 DAC Fullscale Current Register (address = 0x0D) [reset = 0xF000]
      73. 8.5.73 Internal SYSREF Generator Register (address = 0x10) [reset = 0x0000]
      74. 8.5.74 Counter for Internal SYSREF Generator Register (address = 0x11) [reset = 0x0000]
      75. 8.5.75 SPI SYSREF for Internal SYSREF Generator Register (address = 0x12) [reset = 0x0000]
      76. 8.5.76 Digital Test Signals Register (address = 0x1B) [reset = 0x0000]
      77. 8.5.77 Sleep Pin Control Register (address = 0x23) [reset = 0xFFFF]
      78. 8.5.78 SYSREF Capture Circuit Control Register (address = 0x24) [reset = 0x1000]
      79. 8.5.79 Clock Input and PLL Configuration Register (address = 0x31) [reset = 0x0200]
      80. 8.5.80 PLL Configuration 1 Register (address = 0x32) [reset = 0x0308]
      81. 8.5.81 PLL Configuration 2 Register (address = 0x33) [reset = 0x4018]
      82. 8.5.82 LVDS Output Configuration Register (address = 0x34) [reset = 0x0000]
      83. 8.5.83 Fuse Farm clock divider Register (address = 0x35) [reset = 0x0018]
      84. 8.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x0002]
      85. 8.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
      86. 8.5.86 Serdes Configuration 1 Register (address = 0x3D) [reset = 0x0x0088]
      87. 8.5.87 Serdes Configuration 2 Register (address = 0x3E) [reset = 0x0x0909]
      88. 8.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
      89. 8.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Start-up Sequence
    2. 9.2 Typical Application: Multi-band Radio Frequency Transmitter
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Calculating the JESD204B SerDes Rate
        2. 9.2.2.2 Calculating valid JESD204B SYSREF Frequency
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Sequencing
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • AAV|144
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Specifications

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply Voltage Range(2) VDDDAC1, VDDDIG1, VDDL1_1, VDDL2_1, VDDCLK1, VDDT1, VDDCLK1, VDDTX1, VDDE1 –0.3 1.3 V
VDDR18, VDDIO18, VDDS18, VDDAPLL18, VDDOUT18, VDDA18, VDDAVCO18, VDDTX18 –0.3 2.45 V
VEE18N –2 0.3 V
Voltage between AGND and DGND –0.3 0.3 V
Pin Voltage Range(2) RX[0..7]+/- –0.5 VDDDIG1 + 0.5 V V
SDEN, SCLK, SDIO, SDO, TXENABLE, ALARM, RESET, SLEEP, TMS, TCLK, TDI, TDO, TRST, TESTMODE, GPI0, GPI1, GPO0, GPO1 –0.5 VDDIO + 0.5 V V
CLKOUT+/- –0.5 VDDTX18 + 0.5 V V
DACCLK+/-, SYSREF+/-, DACCLKSE –0.5 VDDCLK1 + 0.5 V V
SYNC0+/-, SYNC1+/- –0.5 VDDS18 + 0.5 V V
VOUT1+/-, VOUT2+/- –0.5 VDDAOUT18 + 0.5 V V
RBIAS, EXTIO, ATEST –0.5 VDDAOUT18 + 0.5 V V
IFORCE, VSENSE –0.5 VDDDIG1 + 0.5 V V
AMUX1, AMUX0 –0.5 VDDT1 + 0.5 V V
Peak input current (any input) 20 mA
Peak total input current (all inputs) –30 mA
Junction temperature TJ 150 °C
Operating free-air temperature, TA –40 85 °C
Storage temperature, Tstg –65 150 °C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured with respect to AGND or DGND.

ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
TJ Recommended operating temperature 105 °C
Maximum rated operating junction temperature(1) 125 °C
TA Recommended free-air temperature –40 85 °C
Supply Voltage Range VDDA18, VDDAPLL18, VDDS18, VDDIO18, VDDR18, VDDAPLL18, VDDOUT18, VDDAVCO18 1.71 1.8 1.89 V
VDDDIG1 VDDA1, VDDT1, VDDAPLL1, VDDCLK1, VDDL1_1, VDDL2_1, VDDTX1, VDDE1 0.95 1 1.05 V
VEE18N -1.89 -1.8 -1.71 V
Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate

Thermal Information

THERMAL METRIC(1) AAV (FCBGA) UNIT
144 PINS
RθJA Junction-to-ambient thermal resistance 25 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1.0 °C/W
RθJB Junction-to-board thermal resistance 7.7 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 7.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

Electrical Characteristics - DC Specifications

Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
Resolution 14 bits
DNL Differential nonlinearity (DAC38RF83/93/85) only ±3 LSB
INL Integral nonlinearity (DAC38RF83/93/85) only ±4 LSB
ANALOG OUTPUT
Gain Error (DAC38RF83/93/85) only ±2 %FSR
Full scale output signal current 10 30 40 mA
P(OUTFS) Full scale output power 2:1 transformer coupled into 50 Ω- load. Transformer (TCM2-452X-2+) loss not de-embedded
2.1 GHz output frequency
(DAC38RF83/93/85) only
3 dBm
P(OUTFS) Full scale output power 50-Ω load
2.1 GHz output frequency
(DAC38RF80/90/84) only
0 dBm
Output Compliance Range 1.3 2.3 V
Output capacitance Single ended to ground.
(DAC38RF83/93/85) only
1.5 pF
Output resistance Measured differentially
(DAC38RF83/93/85) only
100 Ω
REFERENCE OUTPUT: EXTIO
VREF Reference output voltage 0.9 V
Reference output current 100 nA
Reference voltage drift ±8 ppm/°C
POWER SUPPLY CURRENT AND CONSUMPTION
1 V Digital supplies: VDDDIG1 MODE 1: 2 TX, 1IQ/slice, LMFS = 8411, PLL on, 12x Interpolation, fINPUT = 737.28 MSPS, fDAC = 8847.36 MSPS, NCO’s = 2.14 GHz, CLKTX Disabled 1478 2290 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 1510 1758 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 281 290 mA
-1.8 V Supply: VEE18N 159 180 mA
PDIS Power Dissipation 3779 4894 mW
1 V Digital supplies: VDDDIG1 MODE 2: 1 TX, 1IQ/slice, LMFS = 4211, PLL on, 12x Interpolation, fINPUT = 737.28 MSPS, fDAC = 8847.36 MSPS, NCO = 2.14 GHz, CLKTX Disabled 1110 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 1303 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 257 mA
-1.8 V Supply: VEE18N 159 mA
PDIS Power Dissipation 3162 mW
1V Digital supplies: VDDDIG1 MODE 3: 2 TX, 2 IQ/slice, LMFS = 8821, PLL on, 24x Interpolation, fINPUT = 368.64 MSPS, fDAC = 8847.36 MSPS, NCO1 = 1.84 GHz, NCO2 = 2.15 GHz, CLKTX Disabled 2253 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 1522 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 280 mA
-1.8 V Supply: VEE18N 159 mA
PDIS Power Dissipation 4565 mW
1 V Digital supplies: VDDDIG1 MODE 4: 1 TX, 2 IQ/slice, LMFS = 4421, PLL on, 24x Interpolation, fINPUT = 368.64 MSPS, fDAC = 8847.36 MSPS, NCO1 = 1.84 GHz, NCO2 = 2.15 GHz, CLKTX Disabled 1701 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 1314 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 256 mA
-1.8 V Supply: VEE18N 159 mA
PDIS Power Dissipation 3763 mW
1 V Digital supplies: VDDDIG1 MODE 5: 2 TX, 1 IQ/slice, LMFS = 4421, PLL on, 18x Interpolation, fINPUT = 491.52 MSPS, fDAC = 8847.36 MSPS, NCO1 = 2.14 GHz, CLKTX Disabled 1328 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 1312 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 249 mA
-1.8 V Supply: VEE18N 159 mA
PDIS Power Dissipation 3374 mW
1 V Digital supplies: VDDDIG1 MODE 6: 1 TX, 1 IQ/slice, LMFS = 2221, PLL on, 18x Interpolation, fINPUT = 491.52 MSPS, fDAC = 8847.36 MSPS, NCO1 = 2.14 GHz, CLKTX Disabled 1027 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 1206 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 248 mA
-1.8 V Supply: VEE18N 159 mA
PDIS Power Dissipation 2964 mW
1 V Digital supplies: VDDDIG1 MODE 7: 2 TX, 1 IQ/slice, LMFS = 8411, PLL on, 6x Interpolation, fINPUT = 983.04 MSPS, fDAC = 5898.24 MSPS, NCO1 = 2.14 GHz, CLKTX Disabled 1157 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 1125 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 246 mA
-1.8 V Supply: VEE18N 159 mA
PDIS Power Dissipation 3011 mW
1 V Digital supplies: VDDDIG1 MODE 8: 1 TX, 1 IQ/slice, LMFS = 4211, PLL on, 6x Interpolation, fINPUT = 983.04 MSPS, fDAC = 5898.24 MSPS, NCO1 = 2.14 GHz, CLKTX Disabled 848 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 647 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 230 mA
-1.8 V Supply: VEE18N 159 mA
PDIS Power Dissipation 2195 mW
1 V Digital supplies: VDDDIG1 MODE 9: 2 TX, 2 IQ/slice, LMFS = 4831, PLL on, 24x Interpolation, fINPUT = 368.64 MSPS, fDAC = 8847.36 MSPS, NCO1 = 2.14 GHz, CLKTX Disabled 2131 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 1324 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 251 mA
-1.8 V Supply: VEE18N 159 mA
PDIS Power Dissipation 4192 mW
1 V Digital supplies: VDDDIG1 MODE 10: 1 TX, 2 IQ/slice, LMFS = 2431, PLL on, 24x Interpolation, fINPUT = 368.64 MSPS, fDAC = 8847.36 MSPS, NCO1 = 2.14 GHz, CLKTX Disabled 1635 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 1212 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 250 mA
-1.8 V Supply: VEE18N 159 mA
PDIS Power Dissipation 3583 mW
1 V Digital supplies: VDDDIG1 MODE 11: Power down mode, no clock, DACs in sleep, SerDes in sleep 63 568 mA
1 V Analog supplies: VDDA1 VDDACLK1 VDDTX1 VDDAPLL1 VDDT1 VDDE1 18 105 mA
1.8 V Supplies: VDDA18 VDDOUT18 VDDAVCO18 VDDAPLL18 VDDR18 VDDIO18 VDDS18 VDDTX18 47 51 mA
-1.8 V Supply: VEE18N 23 28 mA
PDIS Power Dissipation 208 815 mW
VDDTX1 fDAC = 8847 MSPS, Clock Out Divider Enabled 25 mA
fDAC = 5898 MSPS, Clock Out Divider Enabled 19 mA
VDDTX18 Clock Out Enabled 16 mA

Electrical Characteristics - Digital Specifications

Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, nominal supplies, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CML SerDes INPUTS: RX[7:0]+/-
VDIFF Receiver input amplitude 50 1200 mV
VCOM Input common mode voltage TERM = 111 600 mV
TERM = 001 700
TERM = 100 0
TERM = 101 250
ZDDIFF Internal differential termination 85 100 115 Ω
fSerDes SerDes bit rate 0.78125 12.5 Gbps
DIFFERENTIAL CLOCK INPUTS: SYSREF+/-, DACCLK+/-
fDACCLK DACCLK input frequency 0.1 9 GHz
VCOM Differential input common mode voltage 0.5 V
VI(DPP) Differential input peak-to-peak voltage 800 2000 mV
ZT Internal termination 100 Ω
CL Input capacitance 2 pF
Duty cycle (DACCLK only) 40% 60%
LVDS OUTPUT: SYNC0+/-, SYNC1+/-
VCOM Output common mode voltage 1.2 V
ZT Internal termination 100 Ω
VOD Differential output voltage swing 500 mV
CML OUTPUT: CLKTX+/-
VOD CML OUTPUT: CLKTX+/- 1300 mV
CMOS INTERFACE: SDEN, SCLK, SDIO, SDO, TXENABLE, ALARM, RESET, SLEEP, TMS, TCLK, TDI, TDO, TRST, TESTMODE, SYNCSE1, SYNCSE2
VIH High-level input voltage 0.7 x VDDIO V
VIL Low-level input voltage 0.3 x VDDIO V
IIH High-level input current –40 40 µA
IIL Low-level input current –40 40 µA
CI CMOS input capacitance 2 pF
VOH High-level output voltage ILOAD = –100 µA VDDIO – 0.2 V
ILOAD = –2 mA 0.8 x VDDIO
VOL Low-level output voltage ILOAD = 100 µA 0.2 V
ILOAD = 2 mA 0.5
LATENCY
RX SerDes Digital Delay full rate, RATE = “00” 34 UI
half rate, RATE = “01” 29
quarter rate, RATE = “10” 26.5
eighth rate, RATE = “11” 26.25
SerDes output to JED204B elastic buffer input latency 21 - 39 JESD clock cycles
Digital Latency: JESD Buffer to DAC Output LMFSHD = 82121, 6x Interpolation 856 DAC clock cycles
LMFSHD = 82121, 8x Interpolation 1120
LMFSHD = 82121, 12x Interpolation 1602
LMFSHD = 82121, 16x Interpolation 2091
LMFSHD = 42111 or 84111, 6x Interpolation 817
LMFSHD = 42111 or 84111, 8x Interpolation 1057
LMFSHD = 42111 or 84111, 10x Interpolation 1184
LMFSHD = 42111 or 84111, 12x Interpolation 1532
LMFSHD = 42111 or 84111, 16x Interpolation 1997
LMFSHD = 42111 or 84111, 18x Interpolation 2142
LMFSHD = 42111 or 84111, 24x Interpolation 2941
LMFSHD = 22210 or 44210, 8x Interpolation 1020
LMFSHD = 22210 or 44210, 12x Interpolation 1473
LMFSHD = 22210 or 44210, 16x Interpolation 1917
LMFSHD = 22210 or 44210, 18x Interpolation 2050
LMFSHD = 22210 or 44210, 20x Interpolation 2275
LMFSHD = 22210 or 44210, 24x Interpolation 2821
LMFSHD = 12410 or 24410, 16x Interpolation 1912
LMFSHD = 12410 or 24410, 24x Interpolation 2786
LMFSHD = 44210 or 88210, 8x Interpolation 916
LMFSHD = 44210 or 88210, 12x Interpolation 1317
LMFSHD = 44210 or 88210, 16x Interpolation 1709
LMFSHD = 44210 or 88210, 24x Interpolation 2509
LMFSHD = 24410 or 48410, 16x Interpolation 1672
LMFSHD = 24410 or 48410, 24x Interpolation 1593
SYSREF TO JESD LMFC RESET LMFSHD = 82121, 6x Interpolation 5 JESD clock cycles
LMFSHD = 82121, 8x Interpolation 5
LMFSHD = 82121, 12x Interpolation 5
LMFSHD = 82121, 16x Interpolation 5
LMFSHD = 42111 or 84111, 6x Interpolation 16
LMFSHD = 42111 or 84111, 8x Interpolation 16
LMFSHD = 42111 or 84111, 10x Interpolation 15
LMFSHD = 42111 or 84111, 12x Interpolation 15
LMFSHD = 42111 or 84111, 16x Interpolation 13
LMFSHD = 42111 or 84111, 18x Interpolation 15
LMFSHD = 42111 or 84111, 24x Interpolation 15
LMFSHD = 22210 or 44210, 8x Interpolation 8
LMFSHD = 22210 or 44210, 12x Interpolation 7
LMFSHD = 22210 or 44210, 16x Interpolation 6
LMFSHD = 22210 or 44210, 18x Interpolation 7
LMFSHD = 22210 or 44210, 20x Interpolation 5
LMFSHD = 22210 or 44210, 24x Interpolation 4
LMFSHD = 12410 or 24410, 16x Interpolation 9
LMFSHD = 12410 or 24410, 24x Interpolation 7
LMFSHD = 44210 or 88210, 8x Interpolation 29
LMFSHD = 44210 or 88210, 12x Interpolation 27
LMFSHD = 44210 or 88210, 16x Interpolation 26
LMFSHD = 44210 or 88210, 24x Interpolation 25
LMFSHD = 24410 or 48410, 16x Interpolation 8
LMFSHD = 24410 or 48410, 24x Interpolation 6

Electrical Characteristics - AC Specifications

Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, external differential clock mode at
9 GSPS, 12x Interpolation, 0 dBFS, fOUT = 2.14 GHz, I(OUTFS) = 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise noted.
PARAMETER TEST CONDITIONS DAC38RF83/93/85 DAC38RF80/90/84 UNIT
MIN TYP MAX MIN TYP MAX
ANALOG OUTPUT
fDAC Maximum DAC sample rate 9 9 GSPS
AC PERFORMANCE - CW
SFDR Spurious Free Dynamic Range 0 – fDAC/2 fCLK = 6 GHz , fOUT = 501 MHz 63 70 dBc
fCLK = 6 GHz , fOUT = 951 MHz 62 67
fCLK = 6 GHz , fOUT = 1851 MHz 58 59
fCLK = 6 GHz , fOUT = 2651 MHz 57 57
fCLK = 9 GHz , fOUT = 501 MHz 62 64
fCLK = 9 GHz , fOUT = 951 MHz 61 65
fCLK = 9 GHz , fOUT = 1851 MHz 61 62
fCLK = 9 GHz , fOUT = 2651 MHz 54 50
fCLK = 9 GHz , fOUT = 3651 MHz 51 51
SFDR Spurious Free Dynamic Range within 500 MHz fOUT ± 250 MHz fCLK = 6 GHz , fOUT = 501 MHz 97 94 dBc
fCLK = 6 GHz , fOUT = 951 MHz 93 88
fCLK = 6 GHz , fOUT = 1851 MHz 88 87
fCLK = 6 GHz , fOUT = 2651 MHz 77 78
fCLK = 9 GHz , fOUT = 501 MHz 94 92
fCLK = 9 GHz , fOUT = 951 MHz 90 88
fCLK = 9 GHz , fOUT = 1851 MHz 85 85
fCLK = 9 GHz , fOUT = 2651 MHz 82 82
fCLK = 9 GHz , fOUT = 3651 MHz 79 78
SFDR Spurious Free Dynamic Range excluding HD2, HD3 and CMP2 0 – fDAC/2 fCLK = 6 GHz , fOUT = 501 MHz 72 72 dBc
fCLK = 6 GHz , fOUT = 951 MHz 71 75
fCLK = 6 GHz , fOUT = 1851 MHz 74 75
fCLK = 6 GHz , fOUT = 2651 MHz 71 71
fCLK = 9 GHz , fOUT = 501 MHz 69 64
fCLK = 9 GHz , fOUT = 951 MHz 69 66
fCLK = 9 GHz , fOUT = 1851 MHz 72 65
fCLK = 9 GHz , fOUT = 2651 MHz 71 64
fCLK = 9 GHz , fOUT = 3651 MHz 67 62
HD2 2nd Order Harmonic fCLK = 6 GHz , fOUT = 501 MHz 72 71 dBc
fCLK = 6 GHz , fOUT = 951 MHz 65 68
fCLK = 6 GHz , fOUT = 1851 MHz 57 59
fCLK = 6 GHz , fOUT = 2651 MHz 57 57
fCLK = 9 GHz , fOUT = 501 MHz 71 71
fCLK = 9 GHz , fOUT = 951 MHz 65 67
fCLK = 9 GHz , fOUT = 1851 MHz 62 62
fCLK = 9 GHz , fOUT = 2651 MHz 54 49
fCLK = 9 GHz , fOUT = 3651 MHz 51 51
HD3 3rd Order Harmonic fCLK = 6 GHz , fOUT = 501 MHz 63 75 dBc
fCLK = 6 GHz , fOUT = 951 MHz 62 72
fCLK = 6 GHz , fOUT = 1851 MHz 71 72
fCLK = 6 GHz , fOUT = 2651 MHz 69 70
fCLK = 9 GHz , fOUT = 501 MHz 62 74
fCLK = 9 GHz , fOUT = 951 MHz 61 73
fCLK = 9 GHz , fOUT = 1851 MHz 66 72
fCLK = 9 GHz , fOUT = 2651 MHz 65 69
fCLK = 9 GHz , fOUT = 3651 MHz 67 69
CMP2 Fs/2 clock mixing product (Fs/2 – fOUT) fCLK = 6 GHz , fOUT = 501 MHz 85 79 dBc
fCLK = 6 GHz , fOUT = 951 MHz 85 80
fCLK = 6 GHz , fOUT = 1851 MHz 82 76
fCLK = 6 GHz , fOUT = 2651 MHz 79 76
fCLK = 9 GHz , fOUT = 501 MHz 78 70
fCLK = 9 GHz , fOUT = 951 MHz 76 67
fCLK = 9 GHz , fOUT = 1851 MHz 73 67
fCLK = 9 GHz , fOUT = 2651 MHz 74 63
fCLK = 9 GHz , fOUT = 3651 MHz 68 59
CMP4+ Fs/N (N = 4, 8, 16) clock mixing product (fOUT ± Fs/N) fCLK = 6 GHz , fOUT = 501 MHz 92 90 dBc
fCLK = 6 GHz , fOUT = 951 MHz 87 87
fCLK = 6 GHz , fOUT = 1851 MHz 81 83
fCLK = 6 GHz , fOUT = 2651 MHz 78 76
fCLK = 9 GHz , fOUT = 501 MHz 95 91
fCLK = 9 GHz , fOUT = 951 MHz 89 88
fCLK = 9 GHz , fOUT = 1851 MHz 84 85
fCLK = 9 GHz , fOUT = 2651 MHz 79 81
fCLK = 9 GHz , fOUT = 3651 MHz 74 74
IMD3 Third-order two-tone intermodulation distortion fCLK = 6 GHz , fOUT = 501 ± 5 MHz, –6 dBFS each tone 80 83 dBc
fCLK = 6 GHz , fOUT = 951 ± 5 MHz, –6 dBFS each tone 76 79
fCLK = 6 GHz , fOUT = 1851 ± 5 MHz, –6 dBFS each tone 73 76
fCLK = 6 GHz , fOUT = 2651 ± 5 MHz, –6 dBFS each tone 72 75
fCLK = 9 GHz , fOUT = 501 ± 5 MHz, –6 dBFS each tone 80 84
fCLK = 9 GHz , fOUT = 951 ± 5 MHz, –6 dBFS each tone 75 80
fCLK = 9 GHz , fOUT = 1851 ± 5 MHz, –6 dBFS each tone 70 74
fCLK = 9 GHz , fOUT = 2651 ± 5 MHz, –6 dBFS each tone 70 73
fCLK = 9 GHz , fOUT = 3651 ± 5 MHz, –6 dBFS each tone 68 71
NSD Noise Spectral Density > 50 MHz offset
fCLK = 6 GHz , fOUT = 501 MHz –170 –169 dBFS/Hz
fCLK = 6 GHz , fOUT = 951 MHz –163 –163
fCLK = 6 GHz , fOUT = 1851 MHz –157 –155
fCLK = 6 GHz , fOUT = 2651 MHz –155 –154
fCLK = 9 GHz , fOUT = 501 MHz –172 –171
fCLK = 9 GHz , fOUT = 951 MHz –166 –167
fCLK = 9 GHz , fOUT = 1851 MHz –157 –156
fCLK = 9 GHz , fOUT = 2651 MHz –156 –155
fCLK = 9 GHz , fOUT = 3651 MHz –153 –153
fCLK = 6 GHz , fOUT = 501 MHz, –9 dBFS –170 –169
fCLK = 6 GHz , fOUT = 951 MHz, –9 dBFS –164 –163
fCLK = 6 GHz , fOUT = 1851 MHz, –9 dBFS –162 –159
fCLK = 9 GHz , fOUT = 2651 MHz, –9 dBFS –162 –162
fCLK = 9 GHz , fOUT = 3651 MHz, –9 dBFS –159 –159
Isolation Isolation between DAC A and DAC B analog output fOUT = 1856 MHz 82 60 dBc
fOUT = 3105 MHz 73 55
AC PERFORMANCE – Modulated Signals
ACPR WCDMA 1 carrier adjacent channel power ratio fCLK = 5898.24 MHz, fOUT = 950 MHz 76 78 dBc
fCLK = 5898.24 MHz, fOUT = 2140 MHz 75 73
fCLK = 8847.36 MHz, fOUT = 950 MHz 76 77
fCLK = 8847.36 MHz, fOUT = 2140 MHz 73 73
Alt-ACLR WCDMA 1 carrier alternate channel ACPR fCLK = 5898.24 MHz, fOUT = 950 MHz 82 83 dBc
fCLK = 5898.24 MHz, fOUT = 2140 MHz 77 77
fCLK = 8847.36 MHz, fOUT = 950 MHz 82 82
fCLK = 8847.36 MHz, fOUT = 2140 MHz 77 78
LTE20 20 MHz LTE adjacent channel power ratio fCLK = 5898.24 MHz, fOUT = 800 MHz 73 74 dBc
fCLK = 5898.24 MHz, fOUT = 2650 MHz 70 68
fCLK = 8847.36 MHz, fOUT = 800 MHz 73 74
fCLK = 8847.36 MHz, fOUT = 2650 MHz 69 68
fCLK = 8847.36 MHz, fOUT = 3700 MHz 63 66

PLL/VCO Electrical Characteristics

Typical values at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 85°C, internal PLL/VCO clock mode, 12x Interpolation, 0 dBFS, fOUT = 1.8 GHz, I(OUTFS) = 40 mA, nominal supplies, LMFSHd = 84111, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PLL/VCO
fref Reference clock frequency 100 fVCO /4 MHz
fPFD Frequency of phase & frequency detector 100 500 MHz
fvcoL Low VCO operating frequency 5240 6720 MHz
fvcoH High VCO operating frequency 7960 9000 MHz
fBW Loop filter bandwidth 500 KHz
Low VCO Phase Noise
Frequency Offset 600 KHz fvco = 6 GHz,CP = 5, PFD = 500 MHz, measured at output frequency = 1.8 GHz -124 dBc/Hz
1.2 MHz -131
1.8 MHz -135
6.0 MHz -146
High VCO Phase Noise
Frequency Offset 600 KHz fvco = 9 GHz, CP = 5, PFD = 500 MHz, measured at output frequency = 1.8 GHz -123 dBc/Hz
1.2 MHz -131
1.8 MHz -136
6.0 MHz -148

Timing Requirements

MIN NOM MAX UNIT
DIGITAL INPUT TIMING SPECIFICATIONS
TIMING: SYSREF+/-
ts(SYSREF) Setup time, SYSREF+/- valid to rising edge of DACCLK+/- SYSREF Capture assist disabled 50 ps
th(SYSREF) Hold time, SYSREF+/- valid after rising edge of DACCLK+/- SYSREF Capture assist disabled 50 ps
TIMING: SERIAL PORT
ts(/SDEN) Setup time, SDEN to rising edge of SCLK 20 ns
ts(SDIO) Setup time, SDIO valid to rising edge of SCLK 10 ns
th(SDIO) Hold time, SDIO valid after rising edge of SCLK 5 ns
t(SCLK) Period of SCLK temperature sensor read 1 µs
All other registers 100 ns
td(Data) Data output delay after falling edge of SCLK 25 ns
tRESET Minimum RESET pulse width 25 ns
ANALOG OUTPUT
ts(DAC) Output settling time to 0.1% 1 ns
tr Output rise time 10% to 90% 50 ns
tf Output fall time 90% to 10% 50 ns
LATENCY
RX SerDes AnalogDelay 250 ps
DAC wake-up time IOUT current settling to 1% of IOUTFS from deep sleep 90 µs
DAC sleep time IOUT current settling to less than 1% of IOUTFS in deep sleep 90 µs

Typical Characteristics

Unless otherwise noted, all plots are at TA = 25°C, nominal supply voltages, fDAC = 9 GSPS, 12x interpolation, 0 dBFS digital input, 40 mA full scale output current (with 2:1 transformer in DAC38RF83/93/85 only), LMFSHd = 84111 and PLL is disabled.

DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D012_NSDvsDigScale_SLASEA3.gif
Measured 50 MHz from carrier DAC38RF83/93/85
Figure 1. NSD vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D009_NSDvsIFS_SLASEA3.gif
Measured 50 MHz from carrier DAC38RF83/93/85
Figure 3. NSD vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D025_NSDvsClockOption_SLASEA3.gif
Measured 50 MHz from carrier DAC38RF83/93/85
Figure 5. NSD vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D015_HD2vsDigScale_SLASEA3.gif
DAC38RF83/93/85
Figure 7. HD2 vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D021_HD2vsIFS_SLASEA3.gif
DAC38RF83/93/85
Figure 9. HD2 vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D023_HD2vsClockOption_SLASEA3.gif
DAC38RF83/93/85
Figure 11. HD2 vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D016_HD3vsDigScale_SLASEA3.gif
DAC38RF83/93/85
Figure 13. HD3 vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D019_HD3vsIFS_SLASEA3.gif
DAC38RF83/93/85
Figure 15. HD3 vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D024_HD3vsClockOption_SLASEA3.gif
DAC38RF83/93/85
Figure 17. HD3 vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D001_SFDR_no_HD_CMP__DigS_DAC38RFxx_SLASEA3.gif
Excludes HD2, HD3 and CMP2 DAC38RF83/93/85
Figure 19. SFDR vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D001_SFDR_no_HD_CMP__IoutFS_DAC38RFxx_SLASEA3.gif
Excludes HD2, HD3 and CMP2 DAC38RF83/93/85
Figure 21. SFDR vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D001_SFDR_no_HD_CMP__ClockOptions_DAC38RFxx_SLASEA3.gif
Excludes HD2, HD3 and CMP2 DAC38RF83/93/85
Figure 23. SFDR vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D002_SFDR250M_DigS_DAC38RFxx_SLASEA3.gif
±250 MHz Span DAC38RF83/93/85
Figure 25. SFDR vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D002_SFDR250M_IoutFS_DAC38RFxx_SLASEA3.gif
± 250 MHz Span DAC38RF83/93/85
Figure 27. SFDR vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D002_SFDR250M_ClockOptions_DAC38RFxx_SLASEA3.gif
± 250 MHz Span DAC38RF83/93/85
Figure 29. SFDR vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D017_IMD3vsDigScale_SLASEA3.gif
DAC38RF83/93/85
Figure 31. IMD3 vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 IMD3vsIFS_SLASEA3.gif
DAC38RF83/93/85
Figure 33. IMD3 vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D026_IMD3vsClockOption_SLASEA3.gif
DAC38RF83/93/85
Figure 35. IMD3 vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D013_OutputPower_SLASEA3.gif
Transformer loss not de-embedded DAC38RF83/93/85
Figure 37. Power vs Output Frequency
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 RF83_Isolation_SLASEA3.gif
DAC38RF83/93/85
Figure 39. Isolation vs Output Frequency
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D027_9G_nonGSMPLL_SLASEA3.gif
VCO frequency = 8.85 GHz Measured at 1.8 GHz
Figure 41. VCO1 Phase Noise vs Offset Frequency Over Charge pump current
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D029_6G_nonGSMPLL_SLASEA3.gif
VCO frequency = 5.9 GHz Measured at 1.8 GHz
Figure 43. VCO0 Phase Noise vs Offset Frequency Over Charge Pump Current
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D035_NSDvsDigS_DAC38RF80_SLASEA3.gif
Measured 50 MHz from carrier DAC38RF80/90/84
Figure 2. NSD vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D040_NSDvsIFS_DAC38RF80_SLASEA3.gif
Measured 50 MHz from carrier DAC38RF80/90/84
Figure 4. NSD vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D044_NSDvsCLK_DAC38RF80_SLASEA3.gif
Measured 50 MHz from carrier DAC38RF80/90/84
Figure 6. NSD vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D033_HD2vsDigS_DAC38RF80_SLASEA3.gif
DAC38RF80/90/84
Figure 8. HD2 vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D038_HD2vsIFS_DAC38RF80_SLASEA3.gif
DAC38RF80/90/84
Figure 10. HD2 vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D042_HD2vsCLK_DAC38RF80_SLASEA3.gif
DAC38RF80/90/84
Figure 12. HD2 vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D013_HD3vsDigS_nopeaks_RF80.gif
DAC38RF80/90/84
Figure 14. HD3 vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D014_HD3vsIFS_nopeaks_RF80.gif
DAC38RF80/90/84
Figure 16. HD3 vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D015_HD3vsClockOption_nopeaks_RF80.gif
DAC38RF80/90/84
Figure 18. HD3 vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D001_SFDR_no_HD_CMP__DigS_DAC38RF80_SLASEA3.gif
Excludes HD2, HD3 and CMP2 DAC38RF80/90/84
Figure 20. SFDR vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D001_SFDR_no_HD_CMP__IoutFS_DAC38RF80_SLASEA3.gif
Excludes HD2, HD3 and CMP2 DAC38RF80/90/84
Figure 22. SFDR vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D001_SFDR_no_HD_CMP__ClockOptions_DAC38RF80_SLASEA3.gif
Excludes HD2, HD3 and CMP2 DAC38RF80/90/84
Figure 24. SFDR vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D002_SFDR250M_DigS_DAC38RF80_SLASEA3.gif
±250 MHz Span DAC38RF80/90/84
Figure 26. SFDR vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D002_SFDR250M_IoutFS_DAC38RF80_SLASEA3.gif
± 250 MHz Span DAC38RF80/90/84
Figure 28. SFDR vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D002_SFDR250M_ClockOptions_DAC38RF80_SLASEA3.gif
± 250M Hz Span DAC38RF80/90/84
Figure 30. SFDR vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D036_IMD3vsDigS_DAC38RF80_SLASEA3.gif
DAC38RF80/90/84
Figure 32. IMD3 vs Output Frequency Over Input Scale
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 IMD3vsIFS_DAC38RF80_SLASEA3.gif
DAC38RF80/90/84
Figure 34. IMD3 vs Output Frequency Over Output Current IoutFS
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D045_IMD3vsCLK_DAC38RF80_SLASEA3.gif
DAC38RF80/90/84
Figure 36. IMD3 vs Output Frequency Over Clocking Option
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D031_Pout_DAC38RF80_SLASEA3.gif
DAC38RF80/90/84
Figure 38. Power vs Output Frequency
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 RF80_Isolation_SLASEA3.gif
DAC38RF80/90/84
Figure 40. Isolation vs Output Frequency
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D028_9G_nonGSMCLKTX_SLASEA3.gif
VCO frequency = 8.85 GHz
Figure 42. VCO1 Output Clock Phase Noise vs Offset frequency Over Divider Ratio
DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93 D030_6G_nonGSMCLKTX_SLASEA3.gif
VCO frequency = 5.9 GHz
Figure 44. VCO0 Output clock Phase Noise vs Offset Frequency Over Divider Ratio