Top

Product details

Parameters

Resolution (Bits) 14 Sample/update rate (MSPS) 9000 Number of DAC channels (#) 2 Interpolation 10x, 12x, 16x, 18x, 20x, 24x, 6x, 8x Output Single-ended Power consumption (Typ) (mW) 3800 Operating temperature range (C) -40 to 85 open-in-new Find other Transmitters

Package | Pins | Size

FCBGA (AAV) 144 100 mm² 10 x 10 open-in-new Find other Transmitters

Features

  • 14-Bit Resolution
  • Maximum DAC Sample Rate: 9 GSPS
  • Key Specifications:
    • RF Full-Scale Output Power at 2.1 GHz:
      • DAC38RF80/90/84: 0 dBm
      • DAC38RF83/93/85: 3 dBm (with 2:1 balun)
    • Spectral Performance(on-chip PLL, DIFF):
      • fDAC = 5898.24 MSPS, fOUT = 2.14 GHz
        • WCDMA ACLR: 75 dBc
        • WCDMA alt-ACLR: 77 dBc
      • fDAC = 8847.36 MSPS, fOUT = 3.7 GHz
        • 20 MHz LTE ACLR: 63 dBc
      • fDAC = 9 GSPS, fOUT = 1.8 GHz
        • IMD3 = 70 dBc (–6 dBFS, 10-MHz tone spacing)
        • NSD = –157 dBc/Hz
  • Dual-Band Digital Up-converter per DAC
    • 6, 8, 10, 12, 16, 18, 20 or 24x Interpolation
    • 4 Independent NCOs With 48-Bit Resolution
  • JESD204B Interface, Subclass 1
    • Support for Multichip Synchronization
    • Maximum Lane Rate: 12.5 Gbps
  • Single-Ended Output With Integrated Balun (DAC38RF80/90/84) Covering 700 MHz to 3800 MHz
  • Internal PLL and VCO With Bypass
    • fC(VCO) = 5.9 or 8.9 GHz
  • Power Dissipation: 1.4 to 2.2 W/ch
  • Power Supplies: –1.8 V, 1 V, 1.8 V
  • Package: 10 x 10 mm BGA, 0.8 mm Pitch, 144-Balls
open-in-new Find other Transmitters

Description

The DAC38RFxx is a family of high-performance, dual/single-channel, 14-bit, 9-GSPS, RF-sampling digital-to-analog converters (DACs) that are capable of synthesizing wideband signals from 0 to 4.5 GHz. A high dynamic range allows the DAC38RFxx family to generate signals for a wide range of applications including 3G/4G signals for wireless base-stations and radar.

The devices feature a low-power JESD204B Interface with up to 8 lanes with a maximum bit rate of 12.5 Gbps allowing an input data rate of 1.25 GSPS complex per channel. The DAC38RFxx provides two digital up-converters per channel, with multiple options for interpolation rates. A digital quadrature modulator with independent, frequency flexible NCOs are available to support multi-band operation. An optional low-jitter PLL/VCO simplifies the DAC sampling clock generation by allowing use of a lower frequency reference clock.

open-in-new Find other Transmitters
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 14
Type Title Date
* Data sheet DAC38RFxx Dual- or Single-Channel, Single-Ended or Differential Output, 14-Bit, 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip PLL datasheet (Rev. C) Jul. 31, 2017
Application note Impact of Power-Supply Noise on Phase Noise Performance of RF DACs Jun. 13, 2018
Technical article What is a low noise inverting buck converter? Oct. 30, 2017
Technical article An easy power-module reference design for RF data converter negative voltages Oct. 11, 2017
User guide TSW40RF8x Evaluation Module User's Guide (Rev. A) Sep. 27, 2017
Technical article Low-noise charge pumps make it easy to create negative voltages Aug. 30, 2017
Application note Eye Scan Testing with the DAC38RFxx Aug. 10, 2017
Application note Quick-Start Methods in Simulating the DAC38RF8x Input/Output Buffer Information Aug. 02, 2017
Application note DAC38RF8x Test Modes Jul. 25, 2017
Technical article Digital signal processing in RF sampling DACs – part 2 Apr. 04, 2017
User guide DAC38RF8xEVM User's Guide (Rev. A) Mar. 24, 2017
Application note Digital RF Power Control for Power Amplifer Protection in Wireless Base Feb. 06, 2017
Application note RF Sampling DAC with 800 MHz of IBW LTE Oct. 28, 2016
Design guide Efficient Power Supply Scheme for RF-Sampling DAC Reference Design Aug. 22, 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
899
Description

The DAC38RF80EVM is the circuit board for evaluating DAC38RF80/84/90 digital-to-analog converters (DACs). The EVM can be used to evaluate the performance of the DAC up to 9-GSPS sampling rate. It is designed to work with the FPGA-based pattern generator card TSW14J56EVM (Rev B and up). The available (...)

Features
  • Allows evaluation of DAC38RF80/84/90 up to 9-GSPS sampling rate
  • Supports up to 12.5-Gbps SerDes signaling rate across FMC
  • Two on-chip PLLs with superior phase noise to simplify system clock generation; also supports external clock mode
  • AC-coupled output with 2:1 impedance transformer for (...)
EVALUATION BOARD Download
document-generic User guide
2499
Description

The TSW40RF80 evaluation module (EVM) is a two-transmit two-receive (2T2R) RF-sampling transceiver reference design. The module contains the DAC38RF80 dual-channel RF-sampling digital-to-analog converter (DAC) and the ADC32RF45 dual-channel RF-sampling analog-to-digital converter (ADC).

The DAC38RF80 (...)

Features
  • RF-sampling transceiver utilizing the JESD204B interface
  • DAC38RF80 dual RF DAC with single-ended output
  • ADC32RF45 dual RF ADC with bypass option
  • LDO-less power-management solution
  • Onboard clocking solution; four different ADC clocking options, including TX PLL clock output
  • Interfaces with TSW14J56 or (...)

Software development

FIRMWARE Download
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)
FIRMWARE Download
SLAC771A.ZIP (10836 KB)
FIRMWARE Download
SLAC779A.ZIP (48623 KB)
GUI FOR EVALUATION MODULE (EVM) Download
SLAC722D.ZIP (216778 KB)
SUPPORT SOFTWARE Download
High-speed data converter pro software
DATACONVERTERPRO-SW This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Features
  • Compatible with TSW1400, TSW1405, TSW1406, TSW14J10, TSW14J50, TSW14J56, TSW14J57 and TSW14J58 pattern-generation and data-capture platforms
  • Works with all TI high-speed DAC, ADC, and AFE products
  • Provides time-domain and frequency-domain analysis
  • Supports single-tone, multi-tone, and modulated (...)

Design tools & simulation

SIMULATION MODEL Download
SLAM304.ZIP (70 KB) - IBIS Model
SCHEMATIC Download
SLAC734.ZIP (10565 KB)
GERBER FILE Download
SLAC751.ZIP (9967 KB)

Reference designs

REFERENCE DESIGNS Download
Power Supply Reference Design for Optimizing Spur and Phase Noise in RF-sampling DACs
TIDA-01215 — This reference design provides an efficient power supply scheme to power-up the RF-sampling DAC38RF8x digital-to-analog data converter (DAC) without sacrificing performance and also reduces board area and BOM. The reference design uses both DC/DC switchers and an LDO to power-up the DAC38RF8x while (...)
document-generic Schematic
REFERENCE DESIGNS Download
RF-Sampling S-Band Radar Transmitter Reference Design
TIDA-01240 — Synthesis of waveforms appropriate for an S-band multifunction phased array radar (MPAR) is demonstrated with an RF sampling architecture utilizing the DAC38RF80, a 9GSPS 16-bit digital-to-analog converter (DAC). The RF sampling transmit architecture simplifies the signal chain, bringing the data (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
FCBGA (AAV) 144 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos