SLASE48A November   2014  – January 2015 DAC39J84

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  Digital Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serdes Input
      2. 7.3.2  Serdes Rate
      3. 7.3.3  Serdes PLL
      4. 7.3.4  Serdes Equalizer
      5. 7.3.5  JESD204B Descrambler
      6. 7.3.6  JESD204B Frame Assembly
      7. 7.3.7  Serial Peripheral Interface (SPI)
      8. 7.3.8  Multi-Device Synchronization
      9. 7.3.9  Input Multiplexer
      10. 7.3.10 FIR Filters
      11. 7.3.11 Full Complex Mixer
      12. 7.3.12 Coarse Mixer
      13. 7.3.13 Dithering
      14. 7.3.14 Complex Summation
      15. 7.3.15 Quadrature Modulation Correction (QMC)
        1. 7.3.15.1 Gain and Phase Correction
        2. 7.3.15.2 Offset Correction
      16. 7.3.16 Group Delay Correction Block
        1. 7.3.16.1 Fine Fractional Delay FIR Filter
        2. 7.3.16.2 Coarse Fractional Delay FIR Filter
      17. 7.3.17 Output Multiplexer
      18. 7.3.18 Power Measurement And Power Amplifier Protection
      19. 7.3.19 Serdes Test Modes
      20. 7.3.20 Error Counter
      21. 7.3.21 Eye Scan
      22. 7.3.22 JESD204B Pattern Test
      23. 7.3.23 Temperature Sensor
      24. 7.3.24 Alarm Monitoring
      25. 7.3.25 LVPECL Inputs
      26. 7.3.26 CMOS Digital Inputs
      27. 7.3.27 Reference Operation
      28. 7.3.28 Analog Outputs
      29. 7.3.29 DAC Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Clocking Modes
        1. 7.4.1.1 PLL Bypass Mode
        2. 7.4.1.2 PLL Mode
      2. 7.4.2 PRBS TEST MODE
    5. 7.5 Register Map
      1. 7.5.1 Register Descriptions
        1. 7.5.1.1   config0 Register - Address: 0x00, Default: 0x0218
        2. 7.5.1.2   config1 Register - Address: 0x01, Default: 0x0003
        3. 7.5.1.3   config2 Register - Address: 0x02, Default: 0x2002
        4. 7.5.1.4   config3 Register - Address: 0x03, Default: 0xF380
        5. 7.5.1.5   config4 Register - Address: 0x04, Default: 0x00FF
        6. 7.5.1.6   config5 Register - Address: 0x05, Default: 0xFFFF
        7. 7.5.1.7   config6 Register - Address: 0x06, Default: 0xFFFF
        8. 7.5.1.8   config7 Register - Address: 0x07, Default: 0x0000
        9. 7.5.1.9   config8 Register - Address: 0x08, Default: 0x0000
        10. 7.5.1.10  config9 Register - Address: 0x09, Default: 0x0000
        11. 7.5.1.11  config10 Register - Address: 0x0A, Default: 0x0000
        12. 7.5.1.12  config11 Register - Address: 0x0B, Default: 0x0000
        13. 7.5.1.13  config12 Register - Address: 0xC, Default: 0x0400
        14. 7.5.1.14  config13 Register - Address: 0xD, Default: 0x0400
        15. 7.5.1.15  config14 Register - Address: 0x0E, Default: 0x0400
        16. 7.5.1.16  config15 Register - Address: 0x0F, Default: 0x0400
        17. 7.5.1.17  config16 Register - Address: 0x10, Default: 0x0000
        18. 7.5.1.18  config17 Register - Address: 0x11, Default: 0x0000
        19. 7.5.1.19  config18 Register - Address: 0x12, Default: 0x0000
        20. 7.5.1.20  config19 Register - Address: 0x13, Default: 0x0000
        21. 7.5.1.21  config20 Register - Address: 0x14, Default: 0x0000
        22. 7.5.1.22  config21 Register - Address: 0x15, Default: 0x0000
        23. 7.5.1.23  config22 Register - Address: 0x16, Default: 0x0000
        24. 7.5.1.24  config23 Register - Address: 0x17, Default: 0x0000
        25. 7.5.1.25  config24 Register - Address: 0x18, Default: 0x0000
        26. 7.5.1.26  config25 Register - Address: 0x19, Default: 0x0000
        27. 7.5.1.27  config26 Register - Address: 0x1A, Default: 0x0020
        28. 7.5.1.28  config27 Register - Address: 0x1B, Default: 0x0000
        29. 7.5.1.29  config28 Register - Address: 0x1C, Default: 0x0000
        30. 7.5.1.30  config29 Register - Address: 0x1D, Default: 0x0000
        31. 7.5.1.31  config30 Register - Address: 0x1E, Default: 0x1111
        32. 7.5.1.32  config31 Register - Address: 0x1F, Default: 0x1111
        33. 7.5.1.33  config32 Register - Address: 0x20, Default: 0x0000
        34. 7.5.1.34  config33 Register - Address: 0x21, Default: 0x0000
        35. 7.5.1.35  config34 Register - Address: 0x22, Default: 0x1B1B
        36. 7.5.1.36  config35 Register - Address: 0x23, Default: 0xFFFF
        37. 7.5.1.37  config36 Register - Address: 0x24, Default: 0x0000
        38. 7.5.1.38  config37 Register - Address: 0x25, Default: 0x8000
        39. 7.5.1.39  config38 Register - Address: 0x26, Default: 0x0000
        40. 7.5.1.40  config39 Register - Address: 0x27, Default: 0x0000
        41. 7.5.1.41  config40 Register - Address: 0x28, Default: 0x0000
        42. 7.5.1.42  config41 Register - Address: 0x29, Default: 0x0000
        43. 7.5.1.43  config42 Register - Address: 0x2A, Default: 0x0000
        44. 7.5.1.44  config43 Register - Address: 0x2B, Default: 0x0000
        45. 7.5.1.45  config44 Register - Address: 0x2C, Default: 0x0000
        46. 7.5.1.46  config45 Register - Address: 0x2D, Default: 0x0000
        47. 7.5.1.47  config46 Register - Address: 0x2E, Default: 0xFFFF
        48. 7.5.1.48  config47 Register - Address: 0x2F, Default: 0x0004
        49. 7.5.1.49  config48 Register - Address: 0x30, Default: 0x0000
        50. 7.5.1.50  config49 Register - Address: 0x31, Default: 0x0000
        51. 7.5.1.51  config50 Register - Address: 0x32, Default: 0x0000
        52. 7.5.1.52  config51 Register - Address: 0x33, Default: 0x0100
        53. 7.5.1.53  config52 Register - Address: 0x34, Default: 0x0000
        54. 7.5.1.54  config53 Register - Address: 0x35, Default: 0x0000
        55. 7.5.1.55  config54 Register - Address: 0x36, Default: 0x0000
        56. 7.5.1.56  config55 Register - Address: 0x37, Default: 0x0000
        57. 7.5.1.57  config56 Register - Address: 0x38, Default: 0x0000
        58. 7.5.1.58  config57 Register - Address: 0x39, Default: 0x0000
        59. 7.5.1.59  config58 Register - Address: 0x3A, Default: 0x0000
        60. 7.5.1.60  config59 Register - Address: 0x3B, Default: 0x0000
        61. 7.5.1.61  config60 Register - Address: 0x3C, Default: 0x0000
        62. 7.5.1.62  config61 Register - Address: 0x3D, Default: 0x0000
        63. 7.5.1.63  config62 Register - Address: 0x3E, Default: 0x0000
        64. 7.5.1.64  config63 Register - Address: 0x3F, Default: 0x0000
        65. 7.5.1.65  config64 Register - Address: 0x40, Default: 0x0000
        66. 7.5.1.66  config65 Register - Address: 0x41, Default: 0x0000
        67. 7.5.1.67  config66 Register - Address: 0x42, Default: 0x0000
        68. 7.5.1.68  config67 Register - Address: 0x43, Default: 0x0000
        69. 7.5.1.69  config68 Register - Address: 0x44, Default: 0x0000
        70. 7.5.1.70  config69 Register - Address: 0x45, Default: 0x0000
        71. 7.5.1.71  config70 Register - Address: 0x46, Default: 0x0120
        72. 7.5.1.72  config71 Register - Address: 0x47, Default: 0x3450
        73. 7.5.1.73  config72 Register - Address: 0x48, Default: 0x31C3
        74. 7.5.1.74  config73 Register - Address: 0x49, Default: 0x0000
        75. 7.5.1.75  config74 Register - Address: 0x4A, Default: 0x001E
        76. 7.5.1.76  config75 Register - Address: 0x4B, Default: 0x0000
        77. 7.5.1.77  config76 Register - Address: 0x4C, Default: 0x0000
        78. 7.5.1.78  config77 Register - Address: 0x4D, Default: 0x0300
        79. 7.5.1.79  config78 Register - Address: 0x4E, Default: 0x0F0F
        80. 7.5.1.80  config79 Register - Address: 0x4F, Default: 0x1CC1
        81. 7.5.1.81  config80 Register - Address: 0x50, Default: 0x0000
        82. 7.5.1.82  config81 Register - Address: 0x51, Default: 0x00FF
        83. 7.5.1.83  config82 Register - Address: 0x52, Default: 0x00FF
        84. 7.5.1.84  config83 Register - Address: 0x53, Default: 0x0000
        85. 7.5.1.85  config84 Register - Address: 0x54, Default: 0x00FF
        86. 7.5.1.86  config85 Register - Address: 0x55, Default: 0x00FF
        87. 7.5.1.87  config86 Register - Address: 0x56, Default: 0x0000
        88. 7.5.1.88  config87 Register - Address: 0x57, Default: 0x00FF
        89. 7.5.1.89  config88 Register - Address: 0x58, Default: 0x00FF
        90. 7.5.1.90  config89 Register - Address: 0x59, Default: 0x0000
        91. 7.5.1.91  config90 Register - Address: 0x5A, Default: 0x00FF
        92. 7.5.1.92  config91 Register - Address: 0x5B, Default: 0x00FF
        93. 7.5.1.93  config92 Register - Address: 0x5C, Default: 0x1111
        94. 7.5.1.94  config93 Register - Address: 0x5D, Default: 0x0000
        95. 7.5.1.95  config94 Register - Address: 0x5E, Default: 0x0000
        96. 7.5.1.96  config95 Register - Address: 0x5F, Default: 0x0123
        97. 7.5.1.97  config96 Register - Address: 0x60, Default: 0x4567
        98. 7.5.1.98  config97 Register - Address: 0x61, Default: 0x000F
        99. 7.5.1.99  config98 Register - Address: 0x62, Default: 0x0000
        100. 7.5.1.100 config99 Register - Address: 0x63, Default: 0x0000
        101. 7.5.1.101 config100 Register - Address: 0x64, Default: 0x0000
        102. 7.5.1.102 config101 Register - Address: 0x65, Default: 0x0000
        103. 7.5.1.103 config102 Register - Address: 0x66, Default: 0x0000
        104. 7.5.1.104 config103 Register - Address: 0x67, Default: 0x0000
        105. 7.5.1.105 config104 Register - Address: 0x68, Default: 0x0000
        106. 7.5.1.106 config105 Register - Address: 0x69, Default: 0x0000
        107. 7.5.1.107 config106 Register - Address: 0x6A, Default: 0x0000
        108. 7.5.1.108 config107 Register - Address: 0x6B, Default: 0x0000
        109. 7.5.1.109 config108 Register - Address: 0x6C, Default: 0x0000
        110. 7.5.1.110 config109 Register - Address: 0x6D, Default: 0x00xx
        111. 7.5.1.111 config110 Register - Address: 0x6E, Default: 0x0000
        112. 7.5.1.112 config111 Register - Address: 0x6F, Default: 0x0000
        113. 7.5.1.113 config112 Register - Address: 0x70, Default: 0x0000
        114. 7.5.1.114 config113 Register - Address: 0x71, Default: 0x0000
        115. 7.5.1.115 config114 Register - Address: 0x72, Default: 0x0000
        116. 7.5.1.116 config115 Registe - Address: 0x73, Default: 0x0000
        117. 7.5.1.117 config116 Register - Address: 0x74, Default: 0x0000
        118. 7.5.1.118 config117 Register - Address: 0x75, Default: 0x0000
        119. 7.5.1.119 config118 Register - Address: 0x76, Default: 0x0000
        120. 7.5.1.120 config119 Register - Address: 0x77, Default: 0x0000
        121. 7.5.1.121 config120 Register - Address: 0x78, Default: 0x0000
        122. 7.5.1.122 config121 Register - Address: 0x79, Default: 0x0000
        123. 7.5.1.123 config122 Register - Address: 0x7A, Default: 0x0000
        124. 7.5.1.124 config123 Register - Address: 0x7B, Default: 0x0000
        125. 7.5.1.125 config124 Register - Address: 0x7C, Default: 0x0000
        126. 7.5.1.126 config125 Register - Address: 0x7D, Default: 0x0000
        127. 7.5.1.127 config126 Register - Address: 0x7E, Default: 0x0000
        128. 7.5.1.128 config127 Register - Address: 0x7F, Default: 0x0009
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Dual Low-IF Wideband LTE Transmitter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Data Input Rate
          2. 8.2.1.2.2 Intermediate Frequency
          3. 8.2.1.2.3 Interpolation
          4. 8.2.1.2.4 DAC PLL Setup
          5. 8.2.1.2.5 Serdes Lanes
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Dual Zero-IF Wideband Transmitter
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Data Input Rate
          2. 8.2.2.2.2 Interpolation
          3. 8.2.2.2.3 Serdes Lanes
          4. 8.2.2.2.4 LO Feedthrough and Sideband Correction
        3. 8.2.2.3 Application Performance Plots
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

144-Ball Flip Chip BGA
AAV Package
(Top View)
po_lase16.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NUMBER
ALARM L8 O CMOS output for ALARM condition. The ALARM output functionality is defined through the config7 register. Default polarity is active high, but can be changed to active high via config0 alarm_out_pol control bit. If not used it can be left open.
AMUX0 H3 I/O Analog test pin for SerDes, Lane 0 to Lane 3. It can be left open if not used.
AMUX1 E3 I/O Analog test pin for SerDes, Lane 4 to Lane 7. It can be left open if not used.
ATEST K9 I/O Analog test pin for DAC, references and PLL. It can be left open if not used.
DACCLKP A10 I Positive LVPECL clock input for DAC core with Vcm = 0.5V. It can be PLL reference clock or external DAC sampling rate clock. If not used, DACCLK is self-biased with 100mV differential at Vcm = 0.5V.
DACCLKN A9 I Complementary LVPECL clock input for DAC core. (see the DACCLKP description)
EXTIO F10 I/O Used as external reference input when internal reference is disabled through config27 extref_ena = ‘1’. Used as internal reference output when config27 extref_ena = ‘0’ (default). Requires a 0.1 μF decoupling capacitor to analog GND when used as reference output. It can be left open if not used.
GND A12, F12, G12, M12, A11, B11, C11, D11, E11, F11, G11, H11, J11, K11, L11, M11, C8, D8, E8, F8, G8, H8, J8, E7, F7, G7, H7, E6, F6, G6, H6, A5, B5, E5, F5, G5, H5, A4, B4, M4, B3, C3, L3, B2, C2, D2, E2, H2, J2, K2, L2 I These pins are ground for all supplies.
IFORCE C5 I/O Analog test pin for on chip parametric. It can be left open if not used.
IOUTAP B12 O A-Channel DAC current output. Must be tied to GND if not used.
IOUTAN C12 O A-Channel DAC complementary current output. Must be tied to GND if not used.
IOUTBP E12 O B-Channel DAC current output. Must be tied to GND if not used.
IOUTBN D12 O B-Channel DAC complementary current output. Must be tied to GND if not used.
IOUTCP H12 O C-Channel DAC current output. Must be tied to GND if not used.
IOUTCN J12 O C-Channel DAC complementary current output. Must be tied to GND if not used.
IOUTDP L12 O D-Channel DAC current output. Must be tied to GND if not used.
IOUTDN K12 O D-Channel DAC complementary current output. Must be tied to GND if not used.
LPF C9 I/O External PLL loop filter connection. It can be left open if not used.
RBIAS G10 O Full-scale output current bias. Change the full-scale output current through coarse_dac(3:0). Expected to be 1.92kΩ to GND.
RESETB K8 I Active low input for chip RESET, which resets all the programming registers to their default state. Internal pull-up. It can be left open if not used.
RX0P G1 I CML SerDes interface lane 0 input, positive, expected to be AC coupled. It can be left open if not used.
RX0N H1 I CML SerDes interface lane 0 input, negative, expected to be AC coupled. It can be left open if not used.
RX1P K1 I CML SerDes interface lane 1 input, positive, expected to be AC coupled. It can be left open if not used.
RX1N J1 I CML SerDes interface lane 1 input, negative, expected to be AC coupled. It can be left open if not used.
RX2P L1 I CML SerDes interface lane 2 input, positive, expected to be AC coupled. It can be left open if not used.
RX2N M1 I CML SerDes interface lane 2 input, negative, expected to be AC coupled. It can be left open if not used.
RX3P M3 I CML SerDes interface lane 3 input, positive, expected to be AC coupled. It can be left open if not used.
RX3N M2 I CML SerDes interface lane 3 input, negative, expected to be AC coupled. It can be left open if not used.
RX4P F1 I CML SerDes interface lane 4 input, positive, expected to be AC coupled. It can be left open if not used.
RX4N E1 I CML SerDes interface lane 4 input, negative, expected to be AC coupled. It can be left open if not used.
RX5P C1 I CML SerDes interface lane 5 input, positive, expected to be AC coupled. It can be left open if not used.
RX5N D1 I CML SerDes interface lane 5 input, negative, expected to be AC coupled. It can be left open if not used.
RX6P B1 I CML SerDes interface lane 6 input, positive, expected to be AC coupled. It can be left open if not used.
RX6N A1 I CML SerDes interface lane 6 input, negative, expected to be AC coupled. It can be left open if not used.
RX7P A3 I CML SerDes interface lane 7 input, positive, expected to be AC coupled. It can be left open if not used.
RX7N A2 I CML SerDes interface lane 7 input, negative, expected to be AC coupled. It can be left open if not used.
SYSREFP A7 I LVPECL SYSREF positive input with Vcm = 0.5V. This positive/negative pair is captured with the rising edge of DACCLKP/N. It is used for JESD204B Subclass 1 deterministic latency and multiple DAC synchronization, which can be periodic or pulsed. If not used, it is self-biased with 100mV differential at Vcm = 0.5V.
SYSREFN A6 I LVPECL SYSREF negative input with Vcm = 0.5V. (See the SYSREFP description)
SCLK L9 I Serial interface clock. Internal pull-down. It can be left open if not used.
SDENB M9 I Active low serial data enable, always an input to the DAC39J84. Internal pull-up. It can be left open if not used.
SDIO L10 I/O Serial interface data. Bi-directional in 3-pin mode (default) and 4-pin mode. Internal pull-down. It can be left open if not used.
SDO M10 O Uni-directional serial interface data in 4-pin mode. The SDO pin is tri-stated in 3-pin interface mode (default). It can be left open if not used.
SLEEP M8 I Active high asynchronous hardware power-down input. Internal pull-down. It can be left open if not used.
SYNCBP B7 O Synchronization request to transmitter, LVDS positive output. It can be left open if not used.
SYNCBN B6 O Synchronization request to transmitter, LVDS negative output. It can be left open if not used.
SYNC_N_AB L6 O Synchronization request to transmitter, CMOS output. Defaults to link 0, but can be programmable for any link. It can be left open if not used.
SYNC_N_CD L7 O Synchronization request to transmitter, CMOS output. Defaults to link 1, but can be programmable for any link. It can be left open if not used.
TCLK K4 I JTAG test clock. It can be left open if not used.
TDI L5 I JTAG test data in. It can be left open if not used.
TDO M5 O JTAG test data out. It can be left open if not used.
TMS L4 I JTAG test mode select. It can be left open if not used.
TRSTB J3 I JTAG test reset. Must be tied to GND to hold the JTAG state machine status reset if the JTAG port is not used.
TXENABLE K5 I To enable analog output data transmission, set sif_txenable in register config3 to “1” or pull CMOS TXENABLE pin to high. Transmit enable active high input. Internal pull-down. To disable analog output, set sif_txenable to “0” and pull CMOS TXENABLE pin to low. The DAC output is forced to midscale. It can be left open if not used.
TESTMODE K3 O This pin is used for factory testing. Internal pull-down. It can be left open if not used.
VDDADAC33 D10, E10, H10, J10, I Analog supply voltage. (3.3V)
VDDAPLL18 B10, B9 I PLL analog supply voltage. (1.8V)
VDDAREF18 C10, K10 I Analog reference supply voltage (1.8V)
VDDCLK09 A8, B8 I Internal clock buffer supply voltage (0.9V). It is recommended to isolate this supply from VDDDIG09.
VDDDAC09 D9, E9, F9, G9, H9, J9 I DAC core supply voltage. (0.9V). It is recommended to isolate this supply from VDDDIG09.
VDDDIG09 J7, J6, D5, J5, D4, E4, F4, G4, H4, J4, D3 I Digital supply voltage. (0.9V). It is recommended to isolate this supply from VDDCLK09 and VDDDAC09.
VDDIO18 K7, K6 I Supply voltage for all digital I/O and CMOS I/O. (1.8V)
VDDR18 F2, G2 I Supply voltage for SerDes (1.8V)
VDDS18 C7, C6 I Supply voltage for LVDS SYNCBP/N (1.8V)
VDDT09 F3, G3 I Supply voltage for SerDes termination (0.9V)
VQPS18 D7, D6 I Fuse supply voltage. This supply pin is also used for factory fuse programming. Connect to 1.8V.
VSENSE C4 I/O Analog test pin for on chip parametric. It can be left open if not used.