DAC39J84

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Quad-Channel, 16-Bit, 2.8-GSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC)

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Product details

Parameters

Resolution (Bits) 16 DAC channels 4 Interface JESD204B Sample/update rate (MSPS) 2800 Features Ultra High Speed Rating Catalog Interpolation 16x, 1x, 2x, 4x, 8x Power consumption (Typ) (mW) 1619 SFDR (dB) 0 Architecture Current Source Operating temperature range (C) -40 to 85 Reference: type Int open-in-new Find other High-speed DACs (>10MSPS)

Package | Pins | Size

FCBGA (AAV) 144 100 mm² 10 x 10 open-in-new Find other High-speed DACs (>10MSPS)

Features

  • Resolution: 16-Bit
  • Maximum Sample Rate: 2.8GSPS
  • Maximum Input Data Rate: 1.25GSPS
  • JESD204B Interface
    • 8 JESD204B Serial Input Lanes
    • 12.5 Gbps Maximum Bit Rate per Lane
    • Subclass 1 Multi-DAC Synchronization
  • On-Chip Very Low Jitter PLL
  • Selectable 1x –16x Interpolation
  • Independent Complex Mixers with 48-bit NCO/
    or ±n×Fs/8
  • Wideband Digital Quadrature Modulator Correction
  • Sinx/x Correction Filters
  • Fractional Sample Group Delay Correction
  • Multi-Band Mode: Digital Summation of Independent
    Complex Signals
  • 3/4-Wire Serial Control Bus (SPI)
  • Integrated Temperature Sensor
  • JTAG Boundary Scan
  • Pin-Compatible with Quad-Channel DAC37J84/
    DAC38J84 Family
  • Power Dissipation: 1.8W at 2.8GSPS
  • Package: 10 mm × 10 mm, 144-Ball Flip-Chip BGA
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Description

The DAC39J84 is a low power, 16-bit, quad-channel, 2.8 GSPS digital to analog converter (DAC) with JESD204B interface.

Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.

The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.

A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.

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Technical documentation

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Type Title Date
* Datasheet DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface datasheet (Rev. A) Jan. 26, 2015
Application notes DAC3xJ8x Device Initialization and SYSREF Configuration Sep. 27, 2017
Selection guides TI Components for Aerospace and Defense Guide (Rev. E) Mar. 22, 2017
User guides DAC3XJ8XEVM User's Guide (Rev. B) Apr. 28, 2016
Application notes System solution for avionics & defense Sep. 23, 2015
Technical articles JESD204B: How to measure and verify your deterministic latency Feb. 27, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
Description

 The DAC39J84EVM is an evaluation module (EVM) designed to evaluate the DAC39J84 high-speed, JESD204B interface DAC. The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use software GUI and USB interface.

The DAC39J84EVM is designed (...)

Features
  • Allows comprehensive testing of the DAC39J84 high-speed, JESD204B interface DAC
  • Transformer-coupled signal path enables direct performance testing of the DAC39J84 outputs
  • Simplified testing using the onboard LMK04828 JESD204B clocking solution for clock generation, jitter cleaning, or distribution
  • Easy (...)
EVALUATION BOARDS Download
Description

The Abaco FMC120 provides four 16-bit analog-to-digital converters (ADCs) and four 16-bit digital-to-analog converters (DACs). The module highlights two products from Texas Instruments: the ADS54J60 two-channel, 16-bit, 1-GSPS ADC (two) and the DAC39J84 four-channel, 16-bit, 2.8-GSPS DAC (one) in a (...)

GUIS FOR EVALUATION MODULES (EVM) Download
SLAC644B.ZIP (219583 KB)
GUIS FOR EVALUATION MODULES (EVM) Download
SLAC661.ZIP (182158 KB)
GUIS FOR EVALUATION MODULES (EVM) Download
SLAC790.ZIP (219583 KB)

Design tools & simulation

SIMULATION MODELS Download
SLAM197.ZIP (50 KB) - IBIS Model

Reference designs

REFERENCE DESIGNS Download
Synchronized Multi-Transmitter Reference Design: Method of Time-Aligning Multiple DACs
TIDA-00996 To further increase the range, data rate, and reliability of modern mobile communications systems, system designers continue to place more emphasis on multiple-antenna transmitter systems to achieve combinations of spatial diversity and spatial multiplexing. Such implementations can further (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
High Bandwidth, High Frequency Transmitter Reference Design
TIDA-00335 This design illustrates the circuit modifications required to support high bandwidth and  high frequency applications using current source DACs like the  DAC38J84 with the TRF3704 modulator.  The TRF3704 is a 6 GHz modulator capable of supporting wide BB bandwidths.  The DAC38J84 (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
FCBGA (AAV) 144 View options

Ordering & quality

Support & training

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