SBASAC8B May   2023  – March 2024 DAC39RF10 , DAC39RFS10

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - AC Specifications
    7. 6.7  Electrical Characteristics - Power Consumption
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 SPI and FRI Timing Diagrams
    11. 6.11 Typical Characteristics: Bandwidth and DC Linearity
    12. 6.12 Typical Characteristics: Single Tone Spectra
    13. 6.13 Typical Characteristics: Dual Tone Spectra
    14. 6.14 Typical Characteristics: Noise Spectral Density
    15. 6.15 Typical Characteristics: Linearity Sweeps
    16. 6.16 Typical Characteristics: Modulated Waveforms
    17. 6.17 Typical Characteristics: Phase and Amplitude Noise
    18. 6.18 Typical Characteristics: Power Dissipation and Supply Currents
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 DAC Output Modes
        1. 7.3.1.1 NRZ Mode
        2. 7.3.1.2 RTZ Mode
        3. 7.3.1.3 RF Mode
        4. 7.3.1.4 DES Mode
      2. 7.3.2 DAC Core
        1. 7.3.2.1 DAC Output Structure
        2. 7.3.2.2 Full-Scale Current Adjustment
      3. 7.3.3 DEM and Dither
      4. 7.3.4 Offset Adjustment
      5. 7.3.5 Clocking Subsystem
        1. 7.3.5.1 SYSREF Frequency Requirements
        2. 7.3.5.2 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
      6. 7.3.6 Digital Signal Processing Blocks
        1. 7.3.6.1 Digital Upconverter (DUC)
          1. 7.3.6.1.1 Interpolation Filters
          2. 7.3.6.1.2 Numerically Controlled Oscillator (NCO)
            1. 7.3.6.1.2.1 Phase-Continuous NCO Update Mode
            2. 7.3.6.1.2.2 Phase-coherent NCO Update Mode
            3. 7.3.6.1.2.3 Phase-sync NCO Update Mode
            4. 7.3.6.1.2.4 NCO Synchronization
              1. 7.3.6.1.2.4.1 JESD204C LSB Synchonization
            5. 7.3.6.1.2.5 NCO Mode Programming
          3. 7.3.6.1.3 Mixer Scaling
        2. 7.3.6.2 Channel Bonder
        3. 7.3.6.3 DES Interpolator
      7. 7.3.7 JESD204C Interface
        1. 7.3.7.1  Deviation from JESD204C Standard
        2. 7.3.7.2  Transport Layer
        3. 7.3.7.3  Scrambler and Descrambler
        4. 7.3.7.4  Link Layer
        5. 7.3.7.5  Physical Layer
        6. 7.3.7.6  Serdes PLL Control
        7. 7.3.7.7  Serdes Crossbar
        8. 7.3.7.8  Multi-Device Synchronization and Deterministic Latency
          1. 7.3.7.8.1 Programming RBD
        9. 7.3.7.9  Operation in Subclass 0 Systems
        10. 7.3.7.10 Link Reset
      8. 7.3.8 Alarm Generation
    4. 7.4 Device Functional Modes
      1. 7.4.1 DUC and DDS Modes
      2. 7.4.2 JESD204C Interface Modes
        1. 7.4.2.1 JESD204C Interface Modes
        2. 7.4.2.2 JESD204C Format Diagrams
          1. 7.4.2.2.1 16-bit Formats
          2. 7.4.2.2.2 12-bit Formats
          3. 7.4.2.2.3 8-bit Formats
      3. 7.4.3 NCO Synchronization Latency
      4. 7.4.4 Data Path Latency
    5. 7.5 Programming
      1. 7.5.1 Using the Standard SPI Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Serial Interface Protocol
        6. 7.5.1.6 Streaming Mode
      2. 7.5.2 Using the Fast Reconfiguration Interface
      3. 7.5.3 SPI Register Map
  9. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Startup Procedure for DUC/Bypass Mode
      2. 8.1.2 Startup Procedure for DDS Mode
      3. 8.1.3 Eye Scan Procedure
      4. 8.1.4 Pre/Post Cursor Analysis Procedure
      5. 8.1.5 Understanding Dual Edge Sampling Modes
      6. 8.1.6 Sleep and Disable Modes
    2. 8.2 Typical Application
      1. 8.2.1 S-Band Radar Transmitter
        1. 8.2.1.1 System Schematic
        2. 8.2.1.2 Design Requirements
        3. 8.2.1.3 Detailed Transmitter Design Procedure
        4. 8.2.1.4 Detailed Clocking Subsystem Design Procedure
          1. 8.2.1.4.1 Example 1: SWAP-C Optimized
          2. 8.2.1.4.2 Example 2: Improved Phase Noise LMX2820 with External VCO
          3. 8.2.1.4.3 Example 3: Discrete Analog PLL for Best DAC Performance
          4. 8.2.1.4.4 10 GHz Clock Generation
        5. 8.2.1.5 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Up and Down Sequence
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines and Example
  10. Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)

The SYSREF Windowing block is used to first detect the position of SYSREF relative to the input clock CLK± rising edge. Based on the window information, an optimum SYSREF sampling time is selected to maximize setup and hold timing margins relative to the input clock. In many cases a single SYSREF sampling position SYSREF_SEL is sufficient to meet timing for all systems (device-to-device variation) and conditions (temperature and voltage variations). However, this feature can also be used by the system to expand the timing window by tracking the movement of SYSREF as operating conditions change or to remove system-to-system variation at production test by finding a unique optimal value at nominal conditions for each system.

This section describes proper usage of the SYSREF Windowing block (SYSREF_RECV_SLEEP must be programmed to 0). First, apply the device clock and SYSREF to the device. The location of SYSREF relative to the device clock cycle is determined and stored in the SYSREF_POS field. Each bit of SYSREF_POS represents a potential SYSREF sampling position. If a bit in SYSREF_POS is set to 1, then the corresponding SYSREF sampling position has a potential setup or hold violation. Upon determining the valid SYSREF sampling positions (the positions of SYSREF_POS that are set to 0) the desired sampling position can be chosen by setting SYSREF_SEL to the value corresponding to that SYSREF_POS position. In general, the middle sampling position between two setup and hold instances is chosen. Ideally, the determination of SYSREF_SEL is performed at the nominal operating conditions of the system (temperature and supply voltage) to provide maximum margin for operating condition variations. This process can be performed at final test and the optimal SYSREF_SEL setting can be stored for use at every system power up. Further, SYSREF_POS can be used to characterize the skew between CLK± and SYSREF± over operating conditions for a system by sweeping the system temperature and supply voltages. For systems that have large variations in CLK± to SYSREF± skew, this characterization can be used to track the optimal SYSREF sampling position as system operating conditions change. In general, a single value can be found that meets timing over all conditions for well-matched systems, such as those where CLK± and SYSREF± come from a single clocking device.

The step size between each SYSREF_POS sampling position can be adjusted using SYSREF_ZOOM. When SYSREF_ZOOM is set to 0, the delay steps are coarser. When SYSREF_ZOOM is set to 1, the delay steps are finer. See the electrical specifications table for delay step sizes when SYSREF_ZOOM is enabled and disabled. In general, SYSREF_ZOOM is recommended to always be used (SYSREF_ZOOM = 1) unless a transition region (defined by 1's in SYSREF_POS) is not observed, which can be the case for low clock rates. Bits 0 and 19 of SYSREF_POS are always 1 because there is insufficient information to determine if these settings are close to a timing violation, although the actual valid window can extend beyond these sampling positions. The value programmed into SYSREF_SEL is the decimal number representing the desired bit location in SYSREF_POS. Table 7-4 lists some example SYSREF_POS readings and the optimal SYSREF_SEL settings. Although 20 sampling positions are provided by the SYSREF_POS status register, SYSREF_SEL only allows selection of the first 16 sampling positions, corresponding to SYSREF_POSbits 0 to 15. The additional SYSREF_POS status bits are intended only to provide additional knowledge of the SYSREF valid window. In general, lower values of SYSREF_SEL are selected because of delay variation over supply voltage, however in the fourth example a value of 14 provides additional margin and can be selected instead.

If SYSREF_PS_EN is set to 0, only the last SYSREF edge is used for the SYSREF_POS values. Setting SYSREF_PS_EN to 1 enables an "infinite persistence" mode, where if any SYSREF edge since SYSREF_PS_EN is enabled has a 1 in a position, the SYSREF_POS value is set to one. This provides worst case values for SYSREF_POS to select the optimum SYSREF_SEL setting.

Table 7-4 Examples of SYSREF_POS Readings and SYSREF_SEL Selections
SYSREF_POS[19:0]OPTIMAL SYSREF_SEL SETTING
0x092[3:0]
(positions 19-16)
0x091[7:0](1)(positions 15-8)0x090[7:0](1)
(positions 7-0)
b1000b01100000b000110018 or 9
b1000b00000000b0011000112
b1000b01100000b000000016 or 7
b1000b00000011b000000014 or 14
b1100b01100011b000110016
Underlined 0 indicates the bits that are selected, as given in the last column of this table.

To use SYSREF Windowing:

  1. Apply SYSREF and CLK
  2. Set SYSREF_RECV_SLEEP = 0 and SYSREF_ZOOM = 1
  3. If persistence is desired, set SYSREF_PS_EN = 1 and allow many SYSREF transitions for SYSREF_POS to build.
  4. Read SYSREF_POS and determine a proper setting for SYSREF_SEL, as shown above. If a proper sampling point cannot be determined, set SYSREF_ZOOM = 0 and retry.
  5. Once a propoer value for SYSREF_SEL is applied, program SYSREF_PROC_EN = 1 and SYSREF_ALIGN_EN = 1.
  6. SYSREF is not being propoerly processd by the device and the user can proceed to use the JESD204C interface (or other functionality) that relies on SYSREF.
  7. SYSREF may need to be adjusted over large temperature or supply voltage swings, depending on the input clock frequency. The SYSREF invalid window dependence on temperature (tINV(TEMP)) and VA11 supply voltage (tINV(VA11)) is given in Section 6.8. To adjust SYSREF_SEL to track shifts in SYSREF relative to the input clock, the following steps can be looped (i.e. in background during operation of the JESD204C link):
    1. If persistence is desired,clear and then set SYSREF_PS_EN and allow many SYSREF transitions for the SYSREF_POS data to build.
    2. Read SYSREF_POS and determine a new value for SYSREF_SEL (but do not program it yet). The procedure to incrementally adjust SYSREF_SEL should prefer values that are closer to the previousSYSREF_SEL value rather than selecting the smallest valid SYSREF_SEL value. This helps ensure that the original valid window is selected and tracked rather than selecting a different window which would cause clock realignment to occur.
    3. Program SYSREF_PROC_EN = 0. Write the new SYSREF_SEL value, and then set SYSREF_PROC_EN = 1. The new SYSREF_SEL value is now used by the device.
    4. Wait for some period of time, then return to step 7a above.