SLASED6D April   2016  – December 2017 DAC60004 , DAC70004 , DAC80004

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 DACx0004 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Amplifier
      2. 8.3.2 Reference Buffer
      3. 8.3.3 Power-On Reset
        1. 8.3.3.1 POR Pin Feature
        2. 8.3.3.2 Internal Power-On Reset (IPOR) Levels
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface
        1. 8.4.1.1 Stand-Alone Mode
          1. 8.4.1.1.1 SYNC Interrupt - Stand-Alone Mode
          2. 8.4.1.1.2 Read-Back Mode
        2. 8.4.1.2 Daisy-Chain Mode
          1. 8.4.1.2.1 SYNC Interrupt - Daisy-Chain Mode
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 DAC Power-Down Modes
      4. 8.4.4 CLR Pin Functionality and Software CLEAR Mode
        1. 8.4.4.1 DAC Clear Mode Registers
      5. 8.4.5 LDAC Pin Functionality
        1. 8.4.5.1 Software LDAC Mode Registers
      6. 8.4.6 Software Reset Mode
      7. 8.4.7 Output Short Circuit Limit Register
      8. 8.4.8 Status Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Digitally Controlled Asymmetric Bipolar Output
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

14-Pin VSON
DMD Package
Top View
14-Pin TSSOP
PW Package
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NUMBER
CLR 9 Digital Input Clear DAC pin, falling edge sensitive
GND 12 Power Ground
LDAC 1 Digital Input Load DAC pin, active low
POR 6 Digital Input Power-on-reset configuration, Connecting the POR pin to GND powers up all four DACs to zero scale. Connecting this pin to VDD powers up all four DACs to midscale.
REFIN 7 Analog Input Voltage reference input for all channels
SCLK 14 Digital Input Serial interface shift clock
SDIN 13 Digital Input Serial interface digital input
SDO 8 Digital Output Serial interface digital output for readback and daisy chaining
SYNC 2 Digital Input Serial interface synchronization, active low
VDD 3 Power Positive power supply (2.7 V to 5.5 V)
VOUTA 4 Analog Output DAC A output
VOUTB 11 Analog Output DAC B output
VOUTC 5 Analog Output DAC C output
VOUTD 10 Analog Output DAC D output