SLASED6D April   2016  – December 2017 DAC60004 , DAC70004 , DAC80004

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 DACx0004 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Amplifier
      2. 8.3.2 Reference Buffer
      3. 8.3.3 Power-On Reset
        1. 8.3.3.1 POR Pin Feature
        2. 8.3.3.2 Internal Power-On Reset (IPOR) Levels
    4. 8.4 Device Functional Modes
      1. 8.4.1 Serial Interface
        1. 8.4.1.1 Stand-Alone Mode
          1. 8.4.1.1.1 SYNC Interrupt - Stand-Alone Mode
          2. 8.4.1.1.2 Read-Back Mode
        2. 8.4.1.2 Daisy-Chain Mode
          1. 8.4.1.2.1 SYNC Interrupt - Daisy-Chain Mode
      2. 8.4.2 SPI Shift Register
      3. 8.4.3 DAC Power-Down Modes
      4. 8.4.4 CLR Pin Functionality and Software CLEAR Mode
        1. 8.4.4.1 DAC Clear Mode Registers
      5. 8.4.5 LDAC Pin Functionality
        1. 8.4.5.1 Software LDAC Mode Registers
      6. 8.4.6 Software Reset Mode
      7. 8.4.7 Output Short Circuit Limit Register
      8. 8.4.8 Status Register
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application - Digitally Controlled Asymmetric Bipolar Output
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Voltage, VDD to GND –0.3 7 V
Voltage, digital input or output to GND –0.3 VDD + 0.3 V
Voltage, analog input (REFIN) or output (VOUTx) to GND –0.3 VDD + 0.3 V
Input current to any pin except supply pins –10 10 mA
Maximum junction temperature 150 °C
Storage temperature range, Tstg -60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Voltage, VDD to GND 2.7 5.5 V
Voltage, analog input (REFIN) or output (VOUTx) to GND 2.7 V ≤ VDD ≤ 4.5 V 2.2 VDD – 0.2 V
4.5 V ≤ VDD ≤ 5.5 V 2.2 VDD V
Ambient Operating Temperature, TA -40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) DACx0004 UNIT
DMD (VSON) PW (TSSOP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 39.6 99.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 27.3 23.4 °C/W
RθJB Junction-to-board thermal resistance 9.0 42.8 °C/W
ψJT Junction-to-top characterization parameter 0.3 0.9 °C/W
ψJB Junction-to-board characterization parameter 8.9 42.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.5 N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

All minimum/maximum specifications at TA = -40°C to +125°C, 2.7 V ≤ VDD ≤ 5.5 V, 2.5 V ≤ REFIN(4) ≤ VDD, Rload = 5 kΩ to GND, Cload = 200 pF to GND (unless otherwise noted), Digital inputs held at 0 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE(2)
Resolution DAC80004 16 Bits
DAC70004 14
DAC60004 12
INL Relative accuracy(1) ±1 LSB
DNL Differential nonlinearity(1) Ensured monotonic ±1 LSB
TUE Total unadjusted error(1) TA = +20°C to +40°C 1.5 mV
TA = –40°C to +125°C 2
ZCE Zero code error TA = –40°C to +125°C, Code 0d into DAC ±0.2 ±2 mV
TA = +25°C, Code 0d into DAC ±0.1
ZCE-TC Zero code error TC TA = –40°C to +125°C ±5 µV/°C
OE Offset error(1) TA = +20°C to +40°C ±1.2 mV
TA = –40°C to +125°C ±0.2 ±1.8
TA = +25°C ±0.2
OE-TC Offset error drift TA = –40°C to +125°C ±4 µV/°C
FSE Full-scale error(5) TA = +20°C to +40°C, Code 65535d into DAC ±0.05 %FSR
TA = –40°C to +125°C, Code 65535d into DAC ±0.01 ±0.07 %FSR
TA = +25°C ±0.01
FSE-TC Full-scale error drift(5) TA = –40°C to +125°C ±2 ppm FSR/°C
GE Gain error(1) TA = –40°C to +125°C ±0.005 ±0.05 %FSR
TA = +25°C ±0.005
GE-TC Gain drift TA = –40°C to +125°C ±2 ppm FSR/°C
Output voltage drift vs.Time TA = +25°C, Vout = ¾ of full scale, 1900 hr 20 ppm FSR
Load Regulation TA = +25°C, Vout =Mid Scale 0.003%
PSRR DC Power supply rejection ratio(5) TA = +25°C, Vout = full scale –92 dB
DYNAMIC PERFORMANCE
Output voltage settling time ¼ to ¾ scale and ¾ to ¼ scale settling to ±1 LSB, RL = 5 kΩ, Cload = 200 pF to GND 5.8 8 µs
Slew rate 1.5 V/µs
Power-up time(3) 100 µs
Power-on glitch energy Supply slew rate <5 V/msec 8 mV
Power-off glitch energy DAC in power down mode (1 kΩ-GND), Supply slew rate <5 V/msec 7 mV
Output noise 0.1 Hz to 10 Hz 5 µVpp
100 kHz BW 100 µVRMS
Output noise density Measured at 1 kHz 60 nV/√Hz
Measured at 10 kHz 55
THD Total harmonic distortion REFIN = 3 V ± 0.2 Vpp, Frequency = 10 kHz, DAC at mid scale, specified by design –80 dB
PSRR AC power supply rejection ratio 200 mV 50 Hz and 60 Hz sine wave superimposed on power supply voltage (AC analysis) -90 dB
Code change glitch impulse 1 LSB change around major carry, Software LDAC mode 1 nV-s
Channel-to-channel AC (analog) crosstalk Full-scale swing on adjacent channel, Hardware LDAC mode 1 nV-s
Channel-to-channel DC crosstalk Full-scale swing on adjacent channels, Measured channel at zero scale 1 LSB
Full-scale swing on all channel, Measured channel at zero scale 1
Digital crosstalk DAC code mid scale, Adjacent input buffer change from 0000h to FFFFh or vice versa 0.2 nV-S
Reference feedthrough REFIN = 3 V ± 0.86 Vpp, Frequency = 100 Hz to 100 kHz, DAC at zero scale –85 dB
Digital feedthrough At SCLK = 1 MHz, DAC output static at mid scale 0.2 nV-s
OUTPUT CHARACTERISTICS
Voltage range 0 VDD V
Headroom Output loaded 5 kΩ, DAC code FFFFh 0.1 V
Output loaded 0.5 kΩ, DAC code FFFFh 10 %FSR
RL Resistive load 0.5 kΩ
CL Capacitive load RL = ∞ 1 nF
RL = 5 kΩ 2
RO DC output impedance Normal mode 0.5 Ω
Power down with 100 kΩ network 100 kΩ
Power down with 1 kΩ network 1 kΩ
Short circuit current 36 mA
VOLTAGE REFERENCE INPUT
Reference input range 2.7 V ≤ VDD ≤ 4.5 V 2.2 VDD – 0.2 V
4.5 V ≤ VDD ≤ 5.5 V 2.2 VDD
Reference input current 450 µA
Reference input impedance 15 kΩ
Reference input capacitance 10 pF
MBW Multiplying bandwidth 340 kHz
DIGITAL INPUTS
VIH High-level input voltage 2.3 V
VIL Low-level input voltage 0.7 V
Input leakage 0 < VDIGITAL INPUT < VDD ±1 µA
Pin capacitance 4 pF
DIGITAL OUTPUTS
VOH High-level output voltage IOH = 2 mA VDD – 1 V
VOL Low-level output voltage IOL = 2 mA 0.7 V
Pin capacitance 7 pF
POWER SUPPLY REQUIREMENTS
VDD Supply voltage 2.7 5.5 V
IVDD Supply current TA = –40°C to +125°C, Normal mode 4 5.5 mA
TA = –40°C to +125°C, Power-down mode 3 7 µA
Power dissipation TA = –40°C to +125°C, Normal mode 20 mW
TEMPERATURE RANGE
TA Specified performance –40 125 °C
(1) End point fit between codes Code 512 to Code 65,024 - DAC80004, Code 128 to Code 16,256 - DAC70004, Code 32 to Code 4064 - DAC60004, Output unloaded.
(2) Output unloaded
(3) Time to exit power-down mode into normal mode. Measured from 32nd falling edge SCLK to 90% of DAC final value, Characterized at mid scale.
(4) 200 mV headroom is required between REFIN and VDD when 2.7 V ≤ VDD ≤ 4.5 V.
(5) With 100 mV headroom between DAC output and VDD.

7.6 DACx0004 Timing Requirements

At TA = -40°C to +125°C, Trise = Tfall = 1 nV/sec (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2, SDO pin loaded with 10 pF
4.5 V ≤ VDD ≤ 5.5 V 2.7 V ≤ VDD ≤ 4.5 V UNIT
MIN TYP MAX MIN TYP MAX
SERIAL WRITE and READ
tc SCLK cycle time 20 40 ns
tw1 SCLK high pulse duration 10 20 ns
tw2 SCLK low pulse duration 10 20 ns
tsu SYNC to SCLK falling edge setup time 15 30 ns
tsu1 Data setup time 5 10 ns
th1 Data hold time 5 10 ns
td1 SCLK falling edge to SYNC rising edge delay time 5 10 ns
tw3 Minimum SYNC high pulse duration(1) 25 35 ns
td2 SYNC rising edge to SCLK fall ignore delay time 15 20 ns
tw4 LDAC pulse duration low 20 30 ns
td3 SCLK falling edge to LDAC rising edge delay time 10 20 ns
tw5 CLR minimum pulse duration low 10 20 ns
td4 SCLK falling edge to LDAC falling edge delay time 10 20 ns
tv SCLK rising edge to SDO valid time 18 18 ns
td5 SCLK falling edge to SYNC rising edge delay time 5 10 ns
td6 SYNC rising edge to SCLK rising edge delay time 5 10 ns
td7 SYNC rising edge to LDAC or CLR falling edge delay time 20 40 ns
t19 CLR pulse activation time 20 20 ns
t20 Successive DAC Update 2.4 2.4 µs
(1) Does not include output settling tiime
DAC80004 DAC70004 DAC60004 SLASE44_DACx0004_StandAlone_Timing.gif
(1) Asynchronous LDAC update
(2) Synchronous LDAC update
Figure 1. Stand-Alone Timing
DAC80004 DAC70004 DAC60004 SLASE44_DACx0004_Daisychain_Timing.gif
(1) Asynchronous LDAC update
Figure 2. Daisy-Chain Timing

7.7 Typical Characteristics

At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC outputs unloaded, unless otherwise noted.
DAC80004 DAC70004 DAC60004 D014_slase44.gif
Figure 3. Linearity Error vs Digital Input Code
DAC80004 DAC70004 DAC60004 D028_slase44.gif
DAC load 5 kΩ//200 pF
Figure 5. Linearity Error vs Digital Input Code
DAC80004 DAC70004 DAC60004 D039_slase44.gif
Figure 7. Total Unadjusted Error vs Digital Input Code
DAC80004 DAC70004 DAC60004 D016_slase44.gif
Figure 4. Differential Linearity Error vs Digital Input Code
DAC80004 DAC70004 DAC60004 D021_slase44.gif
DAC load 5 kΩ//200 pF
Figure 6. Differential Linearity Error vs Digital Input Code
DAC80004 DAC70004 DAC60004 D040_slase44.gif
DAC load 5 kΩ//200 pF
Figure 8. Total Unadjusted Error vs Digital Input Code
At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC outputs unloaded, unless otherwise noted.
DAC80004 DAC70004 DAC60004 D031_slase44.gif
DAC load 5 kΩ//200 pF
Figure 9. Linearity Error (Max-Min) vs Temperature
DAC80004 DAC70004 DAC60004 D041_slase44.gif
DAC load 5 kΩ//200 pF
Figure 11. Total Unadjusted Error Max/Min vs Temperature
DAC80004 DAC70004 DAC60004 D008_slase44.gif
Figure 13. Gain Error vs Temperature
DAC80004 DAC70004 DAC60004 D024_slase44.gif
DAC load 5 kΩ//200 pF
Figure 10. Differential Linearity Error (Max-Min) vs Temperature
DAC80004 DAC70004 DAC60004 D001_slase44.gif
Figure 12. Offset Error vs Temperature
DAC80004 DAC70004 DAC60004 D011_slase44.gif
Figure 14. Full Scale Error vs Temperature
At TA = 25°C, VDD = 2.7 V, REFIN = 2.5 V, DAC outputs unloaded, unless otherwise noted.
DAC80004 DAC70004 DAC60004 D015_slase44.gif
Figure 15. Linearity Error vs Digital Input Code
DAC80004 DAC70004 DAC60004 D027_slase44.gif
DAC load 5 kΩ//200 pF
Figure 17. Linearity Error vs Digital Input Code
DAC80004 DAC70004 DAC60004 D037_slase44.gif
Figure 19. Total Unadjusted Error vs Digital Input Code
DAC80004 DAC70004 DAC60004 D017_slase44.gif
Figure 16. Differential Linearity Error vs Digital Input Code
DAC80004 DAC70004 DAC60004 D020_slase44.gif
DAC load 5 kΩ//200 pF
Figure 18. Differential Linearity Error vs Digital Input Code
DAC80004 DAC70004 DAC60004 D038_slase44.gif
DAC load 5 kΩ//200 pF
Figure 20. Total Unadjusted Error vs Digital Input Code
At TA = 25°C, VDD = 2.7 V, REFIN = 2.5 V, DAC output unloaded, unless otherwise noted.
DAC80004 DAC70004 DAC60004 D002_slase44.gif
Figure 21. Offset Error vs Temperature
DAC80004 DAC70004 DAC60004 D012_slase44.gif
Figure 23. Full Scale Error vs Temperature
DAC80004 DAC70004 DAC60004 D023_slase44.gif
DAC load 5 kΩ//200 pF
Figure 25. Differential Linearity Error (Max-Min) vs Power Supply Voltage
DAC80004 DAC70004 DAC60004 D009_slase44.gif
Figure 22. Gain Error vs Temperature
DAC80004 DAC70004 DAC60004 D030_slase44.gif
DAC load 5 kΩ//200 pF
Figure 24. Linearity Error (Max-Min) vs Power Supply Voltage
DAC80004 DAC70004 DAC60004 D003_slase44.gif
Figure 26. Offset Error vs Power Supply Voltage
At TA = 25°C, VDD = 5.5 V, REFIN = 2.5 V, DAC output load = 5 kΩ||200 pF, unless otherwise noted.
DAC80004 DAC70004 DAC60004 D010_slase44.gif
Figure 27. Gain Error vs Power Supply Voltage
DAC80004 DAC70004 DAC60004 D029_slase44.gif
Figure 29. Linearity Error (Max-Min) vs Reference Voltage
DAC80004 DAC70004 DAC60004 D026_slase44.gif
Figure 31. Gain Error (Max) vs Reference Voltage
DAC80004 DAC70004 DAC60004 D013_slase44.gif
Figure 28. Full Scale Error vs Power Supply Voltage
DAC80004 DAC70004 DAC60004 D022_slase44.gif
Figure 30. Differential Linearity Error (Max-Min) vs Reference Voltage
DAC80004 DAC70004 DAC60004 D025_slase44.gif
Figure 32. Full Scale Error (Max) vs Reference Voltage
At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC outputs unloaded, All channels active, unless otherwise noted.
DAC80004 DAC70004 DAC60004 D006_slase44.gif
Figure 33. Power Supply Current vs Digital Input Code
DAC80004 DAC70004 DAC60004 D004_slase44.gif
DAC code = mid-scale code
Figure 35. Power Supply Current vs Temperature
DAC80004 DAC70004 DAC60004 D036_slase44.gif
Figure 37. DAC Output Voltage vs Load Current
DAC80004 DAC70004 DAC60004 D007_slase44.gif
VDD = 2.7 V, REFIN = 2.5 V
Figure 34. Power Supply Current vs Digital Input Code
DAC80004 DAC70004 DAC60004 D005_slase44.gif
REFIN = 2.5 V, DAC code = mid-scale code
Figure 36. Power Supply Current vs Power Supply Voltage
DAC80004 DAC70004 DAC60004 D035_slase44.gif
VDD = 2.7 V, REFIN = 2.5 V
Figure 38. DAC Output Voltage vs Load Current
At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC output load = 5 kΩ||200 pF, unless otherwise noted.
DAC80004 DAC70004 DAC60004 D019_slase44.gif
REFIN = 2.5 V, All channels active with full-scale code, DAC unloaded
Figure 39. DAC Output Voltage vs Power Supply Voltage
DAC80004 DAC70004 DAC60004 D033d_slase44.gif
DAC code transition from 8000h to 7FFFh
Figure 41. Glitch Impulse, Falling Edge, 1LSB Step
DAC80004 DAC70004 DAC60004 Fig45_Settling_time_Rise_5p5_5p45_lase44.gif
From code 512d to 65024d, Typical channel shown
Figure 43. Full-Scale Settling Time, Rising Edge
DAC80004 DAC70004 DAC60004 D032_slase44.gif
DAC unloaded, All channels to mid-scale
Figure 40. Power Supply Current vs Digital Input Pins Logic Level
DAC80004 DAC70004 DAC60004 D034d_slase44.gif
DAC code transition from 7FFFh to 8000h
Figure 42. Glitch Impulse, Rising Edge, 1LSB Step
DAC80004 DAC70004 DAC60004 Fig44_Settling_time_Fall_5p5_5p45_lase44.gif
From code 65024d to 512d, Typical channel shown
Figure 44. Full-Scale Settling Time, Falling Edge
At TA = 25°C, VDD = 5.5 V, REFIN = 5.45 V, DAC output load = 5 kΩ||200 pF, unless otherwise noted.
DAC80004 DAC70004 DAC60004 D048_slase44.gif
DAC unloaded
Figure 45. Power-On Glitch, Reset to Zero Scale
DAC80004 DAC70004 DAC60004 Fig43_SCLK_Feedthrough_5p5_5p45_lase44.gif
DAC unloaded, DAC code mid-scale, Typical channel shown
Figure 47. Clock Feedthrough, 1MHz Midscale
DAC80004 DAC70004 DAC60004 D046_slase44.gif
DAC unloaded, Typical channel shown
Figure 49. DAC Output Noise Density vs Frequency
DAC80004 DAC70004 DAC60004 D047_slase44.gif
DAC in power down mode (1 kΩ-GND)
Figure 46. Power-Off Glitch, Reset to Zero Scale
DAC80004 DAC70004 DAC60004 D018_slase44.gif
VDD = 5.0 + 1 VPP (Sinusoid), REFIN = 2.5 V, DAC code full-scale, Typical channel shown
Figure 48. DAC Output AC PSRR vs VDD
DAC80004 DAC70004 DAC60004 Fig42_DAC_out_noise_pp_5p5_5p45_lase44.gif
DAC unloaded, DAC code mid-scale, Typical channel shown
Figure 50. DAC Output Noise, 0.1 Hz to 10 Hz