The CLR pin enables a simultaneous update of multiple DAC channels to the clear value: zero code (DACx0508ZC) or midscale code (DACx0508MC). DAC channels 0 through 3 and channels 4 through 7 can be independently configured to update or remain unaffected by the CLR pin by setting the corresponding CLR-MSK bit. A CLR pin logic low forces those DAC channels that have been configured for clear operation to clear the contents of their buffer and active registers to the clear value and sets the analog outputs accordingly, regardless of their synchronization setting. Those channels not configured for clear operation retain their buffer and active register contents as well as the corresponding analog outputs even if a clear command is issued. While the CLR pin is kept low, register writes to the DAC data registers of those channels set for clear operation are ignored. A logic high on the CLR pin causes the device to exit clear mode.