SLASEO0B Data sheet

Table 8-7 lists the memory-mapped registers for the device. All register offset addresses not listed in Table 8-7 should be considered as reserved locations and the register contents should not be modified.

Table 8-7 DACx1416 Registers

Offset	Acronym	Register Name	Section
00h	NOP	NOP Register	Go
01h	DEVICEID	Device ID Register	Go
02h	STATUS	Status Register	Go
03h	SPICONFIG	SPI Configuration Register	Go
04h	GENCONFIG	General Configuration Register	Go
05h	BRDCONFIG	Broadcast Configuration Register	Go
06h	SYNCCONFIG	Sync Configuration Register	Go
07h	TOGGCONFIG0	DAC[15:8] Toggle Configuration Register	Go
08h	TOGGCONFIG1	DAC[7:0] Toggle Configuration Register	Go
09h	DACPWDWN	DAC Power-Down Register	Go
0Ah	DACRANGE0	DAC[15:12] Range Register	Go
0Bh	DACRANGE1	DAC[11:8] Range Register	Go
0Ch	DACRANGE2	DAC[7:4] Range Register	Go
0Dh	DACRANGE3	DAC[3:0] Range Register	Go
0Eh	TRIGGER	Trigger Register	Go
0Fh	BRDCAST	Broadcast Data Register	Go
10h	DAC0	DAC0 Data Register	Go
11h	DAC1	DAC1 Data Register	Go
12h	DAC2	DAC2 Data Register	Go
13h	DAC3	DAC3 Data Register	Go
14h	DAC4	DAC4 Data Register	Go
15h	DAC5	DAC5 Data Register	Go
16h	DAC6	DAC6 Data Register	Go
17h	DAC7	DAC7 Data Register	Go
18h	DAC8	DAC8 Data Register	Go
19h	DAC9	DAC9 Data Register	Go
1Ah	DAC10	DAC10 Data Register	Go
1Bh	DAC11	DAC11 Data Register	Go
1Ch	DAC12	DAC12 Data Register	Go
1Dh	DAC13	DAC13 Data Register	Go
1Eh	DAC14	DAC14 Data Register	Go
1Fh	DAC15	DAC15 Data Register	Go
20h	OFFSET0	DAC[14-15;12-13] Differential Offset Register	Go
21h	OFFSET1	DAC[10-11;8-9] Differential Offset Register	Go
22h	OFFSET2	DAC[6-7;4-5] Differential Offset Register	Go
23h	OFFSET3	DAC[2-3;0-1] Differential Offset Register	Go

Complex bit access types are encoded to fit into small table cells. Table 8-8 shows the codes that are used for access types in this section.

Table 8-8 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value
Register Array Variables
i,j,k,l,m,n		When these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
y		When this variable is used in a register name, an offset, or an address it refers to the value of a register array.

8.6.1 NOP Register (Offset = 00h) [reset = 0000h]

NOP is shown in Figure 8-6 and described in Table 8-9.

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Figure 8-6 NOP Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
NOP
W-0h

Table 8-9 NOP Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	NOP	W	0h	No operation. Write 0000h for proper no-operation command.

8.6.2 DEVICEID Register (Offset = 01h) [reset = ----h]

DEVICEID is shown in Figure 8-7 and described in Table 8-10.

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Figure 8-7 DEVICEID Register

15	14	13	12	11	10	9	8
DEVICEID
R----h
7	6	5	4	3	2	1	0
DEVICEID						VERSIONID
R----h						R-0h

Table 8-10 DEVICEID Register Field Descriptions

Bit	Field	Type	Reset	Description
15-2	DEVICEID	R	---h	Device ID DAC81416: 29Ch DAC71416: 28Ch DAC61416: 24Ch
1-0	VERSIONID	R	0h	Version ID. Subject to change.

Bit

Field

Type

Reset

Description

15-2

DEVICEID

R

---h

Device ID

DAC81416: 29Ch

DAC71416: 28Ch

DAC61416: 24Ch

1-0

VERSIONID

R

0h

Version ID. Subject to change.

8.6.3 STATUS Register (Offset = 02h) [reset = 0000h]

STATUS is shown in Figure 8-8 and described in Table 8-11.

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Figure 8-8 STATUS Register

15	14	13	12	11	10	9	8
RESERVED
R-0h
7	6	5	4	3	2	1	0
RESERVED					CRC-ALM	DAC-BUSY	TEMP-ALM
R-0h					R-0h	R-0h	R-0h

Table 8-11 STATUS Register Field Descriptions

Bit	Field	Type	Reset	Description
15-3	RESERVED	R	0h	This bit is reserved.
2	CRC-ALM	R	0h	CRC-ALM = 1 indicates a CRC error.
1	DAC-BUSY	R	0h	DAC-BUSY = 1 indicates DAC registers are not ready for updates.
0	TEMP-ALM	R	0h	TEMP-ALM = 1 indicates die temperature is over +140°C. A thermal alarm event forces the DAC outputs to go into power-down mode.

8.6.4 SPICONFIG Register (Offset = 03h) [reset = 0AA4h]

SPICONFIG is shown in Figure 8-9 and described in Table 8-12.

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Figure 8-9 SPICONFIG Register

15	14	13	12	11	10	9	8
RESERVED				TEMPALM-EN	DACBUSY-EN	CRCALM-EN	RESERVED
R-0h				R/W-1h	R/W-0h	R/W-1h	R-0h
7	6	5	4	3	2	1	0
RESERVED	SOFTTOGGLE-EN	DEV-PWDWN	CRC-EN	STR-EN	SDO-EN	FSDO	RESERVED
R-1h	R/W-0h	R/W-1h	R/W-0h	R/W-0h	R/W-1h	R/W-0h	R-0h

Table 8-12 SPICONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	RESERVED	R	0h	This bit is reserved.
11	TEMPALM-EN	R/W	1h	When set to 1 a thermal alarm triggers the ALMOUT pin.
10	DACBUSY-EN	R/W	0h	When set to 1 the ALMOUT pin is set between DAC output updates. Contrary to other alarm events, this alarm resets automatically.
9	CRCALM-EN	R/W	1h	When set to 1 a CRC error triggers the ALMOUT pin.
8	RESERVED	R	0h	This bit is reserved.
7	RESERVED	R	1h	This bit is reserved.
6	SOFTTOGGLE-EN	R/W	0h	When set to 1 enables soft toggle operation.
5	DEV-PWDWN	R/W	1h	DEV-PWDWN = 1 sets the device in power-down mode DEV-PWDWN = 0 sets the device in active mode
4	CRC-EN	R/W	0h	When set to 1 frame error checking is enabled.
3	STR-EN	R/W	0h	When set to 1 streaming mode operation is enabled.
2	SDO-EN	R/W	1h	When set to 1 the SDO pin is operational.
1	FSDO	R/W	0h	Fast SDO bit (half-cycle speedup). When 0, SDO updates during SCLK rising edges. When 1, SDO updates during SCLK falling edges.
0	RESERVED	R	0h	This bit is reserved.

8.6.5 GENCONFIG Register (Offset = 04h) [reset = 7F00h]

GENCONFIG is shown in Figure 8-10 and described in Table 8-13.

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Figure 8-10 GENCONFIG Register

15	14	13	12	11	10	9	8
RESERVED	REF-PWDWN	RESERVED
R-0h	R/W-1h	R-1h
7	6	5	4	3	2	1	0
DAC-14-15-DIFF-EN	DAC-12-13-DIFF-EN	DAC-10-11-DIFF-EN	DAC-8-9-DIFF-EN	DAC-6-7-DIFF-EN	DAC-4-5-DIFF-EN	DAC-2-3-DIFF-EN	DAC-0-1-DIFF-EN
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 8-13 GENCONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	RESERVED	R	0h	This bit is reserved.
14	REF-PWDWN	R/W	1h	REF-PWDWN = 1 powers down the internal reference REF-PWDWN = 0 activates the internal reference
13-8	RESERVED	R	1h	This bit is reserved.
7	DAC-14-15-DIFF-EN	R/W	0h	When set to 1 the corresponding DAC pair is set to operate in differential mode. The DAC data registers must be rewritten after enabling or disabling differential operation.
6	DAC-12-13-DIFF-EN	R/W	0h
5	DAC-10-11-DIFF-EN	R/W	0h
4	DAC-8-9-DIFF-EN	R/W	0h
3	DAC-6-7-DIFF-EN	R/W	0h
2	DAC-4-5-DIFF-EN	R/W	0h
1	DAC-2-3-DIFF-EN	R/W	0h
0	DAC-0-1-DIFF-EN	R/W	0h

8.6.6 BRDCONFIG Register (Offset = 05h) [reset = FFFFh]

BRDCONFIG is shown in Figure 8-11 and described in Table 8-14.

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Figure 8-11 BRDCONFIG Register

15	14	13	12	11	10	9	8
DAC15-BRDCAST-EN	DAC14-BRDCAST-EN	DAC13-BRDCAST-EN	DAC12-BRDCAST-EN	DAC11-BRDCAST-EN	DAC10-BRDCAST-EN	DAC9-BRDCAST-EN	DAC8-BRDCAST-EN
R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h
7	6	5	4	3	2	1	0
DAC7-BRDCAST-EN	DAC6-BRDCAST-EN	DAC5-BRDCAST-EN	DAC4-BRDCAST-EN	DAC3-BRDCAST-EN	DAC2-BRDCAST-EN	DAC1-BRDCAST-EN	DAC0-BRDCAST-EN
R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h

Table 8-14 BRDCONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	DAC15-BRDCAST-EN	R/W	1h	When set to 1 the corresponding DAC is set to update its output to the value set in the BRDCAST register. All DAC channels must be configured in single-ended mode for broadcast operation. If one or more outputs are configured in differential mode the broadcast mode is ignored. When cleared to 0 the corresponding DAC output remains unaffected by a BRDCAST command.
14	DAC14-BRDCAST-EN	R/W	1h
13	DAC13-BRDCAST-EN	R/W	1h
12	DAC12-BRDCAST-EN	R/W	1h
11	DAC11-BRDCAST-EN	R/W	1h
10	DAC10-BRDCAST-EN	R/W	1h
9	DAC9-BRDCAST-EN	R/W	1h
8	DAC8-BRDCAST-EN	R/W	1h
7	DAC7-BRDCAST-EN	R/W	1h
6	DAC6-BRDCAST-EN	R/W	1h
5	DAC5-BRDCAST-EN	R/W	1h
4	DAC4-BRDCAST-EN	R/W	1h
3	DAC3-BRDCAST-EN	R/W	1h
2	DAC2-BRDCAST-EN	R/W	1h
1	DAC1-BRDCAST-EN	R/W	1h
0	DAC0-BRDCAST-EN	R/W	1h

8.6.7 SYNCCONFIG Register (Offset = 06h) [reset = 0000h]

SYNCCONFIG is shown in Figure 8-12 and described in Table 8-15.

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Figure 8-12 SYNCCONFIG Register

15	14	13	12	11	10	9	8
DAC15-SYNC-EN	DAC14-SYNC-EN	DAC13-SYNC-EN	DAC12-SYNC-EN	DAC11-SYNC-EN	DAC10-SYNC-EN	DAC9-SYNC-EN	DAC8-SYNC-EN
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h
7	6	5	4	3	2	1	0
DAC7-SYNC-EN	DAC6-SYNC-EN	DAC5-SYNC-EN	DAC4-SYNC-EN	DAC3-SYNC-EN	DAC2-SYNC-EN	DAC1-SYNC-EN	DAC0-SYNC-EN
R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h	R/W-0h

Table 8-15 SYNCCONFIG Register Field Descriptions

Bit	Field	Type	Reset	Description
15	DAC15-SYNC-EN	R/W	0h	When set to 1 the corresponding DAC output is set to update in response to an LDAC trigger (synchronous mode). When cleared to 0 the corresponding DAC output is set to update immediately (asynchronous mode).
14	DAC14-SYNC-EN	R/W	0h
13	DAC13-SYNC-EN	R/W	0h
12	DAC12-SYNC-EN	R/W	0h
11	DAC11-SYNC-EN	R/W	0h
10	DAC10-SYNC-EN	R/W	0h
9	DAC9-SYNC-EN	R/W	0h
8	DAC8-SYNC-EN	R/W	0h
7	DAC7-SYNC-EN	R/W	0h
6	DAC6-SYNC-EN	R/W	0h
5	DAC5-SYNC-EN	R/W	0h
4	DAC4-SYNC-EN	R/W	0h
3	DAC3-SYNC-EN	R/W	0h
2	DAC2-SYNC-EN	R/W	0h
1	DAC1-SYNC-EN	R/W	0h
0	DAC0-SYNC-EN	R/W	0h

8.6.8 TOGGCONFIG0 Register (Offset = 07h) [reset = 0000h]

TOGGCONFIG0 is shown in Figure 8-13 and described in Table 8-16.

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Figure 8-13 TOGGCONFIG0 Register

15	14	13	12	11	10	9	8
DAC15-AB-TOGG-EN		DAC14-AB-TOGG-EN		DAC13-AB-TOGG-EN		DAC12-AB-TOGG-EN
R/W-0h		R/W-0h		R/W-0h		R/W-0h
7	6	5	4	3	2	1	0
DAC11-AB-TOGG-EN		DAC10-AB-TOGG-EN		DAC9-AB-TOGG-EN		DAC8-AB-TOGG-EN
R/W-0h		R/W-0h		R/W-0h		R/W-0h

Table 8-16 TOGGCONFIG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	DAC15-AB-TOGG-EN	R/W	0h	Enables toggle mode operation and configures the toggle pin or soft toggle bit: 00 = Toggle mode disabled 01 = Toggle mode enabled: TOGGLE0 10 = Toggle mode enabled: TOGGLE1 11 = Toggle mode enabled: TOGGLE2
13-12	DAC14-AB-TOGG-EN	R/W	0h
11-10	DAC13-AB-TOGG-EN	R/W	0h
9-8	DAC12-AB-TOGG-EN	R/W	0h
7-6	DAC11-AB-TOGG-EN	R/W	0h
5-4	DAC10-AB-TOGG-EN	R/W	0h
3-2	DAC9-AB-TOGG-EN	R/W	0h
1-0	DAC8-AB-TOGG-EN	R/W	0h

8.6.9 TOGGCONFIG1 Register (Offset = 08h) [reset = 0000h]

TOGGCONFIG1 is shown in Figure 8-14 and described in Table 8-17.

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Figure 8-14 TOGGCONFIG1 Register

15	14	13	12	11	10	9	8
DAC7-AB-TOGG-EN		DAC6-AB-TOGG-EN		DAC5-AB-TOGG-EN		DAC4-AB-TOGG-EN
R/W-0h		R/W-0h		R/W-0h		R/W-0h
7	6	5	4	3	2	1	0
DAC3-AB-TOGG-EN		DAC2-AB-TOGG-EN		DAC1-AB-TOGG-EN		DAC0-AB-TOGG-EN
R/W-0h		R/W-0h		R/W-0h		R/W-0h

Table 8-17 TOGGCONFIG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
15-14	DAC7-AB-TOGG-EN	R/W	0h	Enables toggle mode operation and configures the toggle pin or soft toggle bit: 00 = Toggle mode disabled 01 = Toggle mode enabled: TOGGLE0 10 = Toggle mode enabled: TOGGLE1 11 = Toggle mode enabled: TOGGLE2
13-12	DAC6-AB-TOGG-EN	R/W	0h
11-10	DAC5-AB-TOGG-EN	R/W	0h
9-8	DAC4-AB-TOGG-EN	R/W	0h
7-6	DAC3-AB-TOGG-EN	R/W	0h
5-4	DAC2-AB-TOGG-EN	R/W	0h
3-2	DAC1-AB-TOGG-EN	R/W	0h
1-0	DAC0-AB-TOGG-EN	R/W	0h

8.6.10 DACPWDWN Register (Offset = 09h) [reset = FFFFh]

DACPWDWN is shown in Figure 8-15 and described in Table 8-18.

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Figure 8-15 DACPWDWN Register

15	14	13	12	11	10	9	8
DAC15-PWDWN	DAC14-PWDWN	DAC13-PWDWN	DAC12-PWDWN	DAC11-PWDWN	DAC10-PWDWN	DAC9-PWDWN	DAC8-PWDWN
R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h
7	6	5	4	3	2	1	0
DAC7-PWDWN	DAC6-PWDWN	DAC5-PWDWN	DAC4-PWDWN	DAC3-PWDWN	DAC2-PWDWN	DAC1-PWDWN	DAC0-PWDWN
R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h	R/W-1h

Table 8-18 DACPWDWN Register Field Descriptions

Bit	Field	Type	Reset	Description
15	DAC15-PWDWN	R/W	1h	When set to 1 the corresponding DAC is in power-down mode and its output is connected to GND through a 10-kΩ internal resistor.
14	DAC14-PWDWN	R/W	1h
13	DAC13-PWDWN	R/W	1h
12	DAC12-PWDWN	R/W	1h
11	DAC11-PWDWN	R/W	1h
10	DAC10-PWDWN	R/W	1h
9	DAC9-PWDWN	R/W	1h
8	DAC8-PWDWN	R/W	1h
7	DAC7-PWDWN	R/W	1h
6	DAC6-PWDWN	R/W	1h
5	DAC5-PWDWN	R/W	1h
4	DAC4-PWDWN	R/W	1h
3	DAC3-PWDWN	R/W	1h
2	DAC2-PWDWN	R/W	1h
1	DAC1-PWDWN	R/W	1h
0	DAC0-PWDWN	R/W	1h

8.6.11 DACRANGEn Register (Offset = 0Ah - 0Dh) [reset = 0000h]

DACRANGEn is shown in Figure 8-16 and described in Table 8-19.

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Figure 8-16 DACRANGEn Register

15	14	13	12	11	10	9	8
DACa-RANGE[3:0]				DACb-RANGE[3:0]
W-0h				W-0h
7	6	5	4	3	2	1	0
DACc-RANGE[3:0]				DACd-RANGE[3:0]
W-0h				W-0h

Table 8-19 DACRANGEn Register Field Descriptions

Bit	Field	Type	Reset	Description
15-12	DACa-RANGE[3:0]	W	0h	Sets the output range for the corresponding DAC. 0000 = 0 to 5 V 0001 = 0 to 10 V 0010 = 0 to 20 V 0100 = 0 to 40 V 1001 = -5 V to +5 V 1010 = -10 V to +10 V 1100 = -20 V to +20 V 1110 = -2.5 V to +2.5 V All others: invalid The two outputs of a differential DAC pair must be configured to the same output range prior to setting them up as a differential pair. a: 15, 11, 7 or 3; b: 14, 10, 6 or 2; c: 13, 9, 5 or 1; d: 12, 8, 4 or 0
11-8	DACb-RANGE[3:0]	W	0h
7-4	DACc-RANGE[3:0]	W	0h
3-0	DACd-RANGE[3:0]	W	0h

8.6.12 TRIGGER Register (Offset = 0Eh) [reset = 0000h]

TRIGGER is shown in Figure 8-17 and described in Table 8-20.

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Figure 8-17 TRIGGER Register

15	14	13	12	11	10	9	8
RESERVED							ALM-RESET
W-0h							W-0h
7	6	5	4	3	2	1	0
AB-TOG2	AB-TOG1	AB-TOG0	LDAC	SOFT-RESET[3:0]
W-0h	W-0h	W-0h	W-0h	W-0h

Table 8-20 TRIGGER Register Field Descriptions

Bit	Field	Type	Reset	Description
15-9	RESERVED	W	0h	This bit is reserved
8	ALM-RESET	W	0h	Set this bit to 1 to clear an alarm event. Not applicable for a DAC-BUSY alarm event.
7	AB-TOG2	W	0h	If soft toggle is enabled set, this bit controls the toggle between values for those DACs that have been set in toggle mode 2 in the TOGGCONFIG register. Set to 1 to update to Register B and clear to 0 for Register A.
6	AB-TOG1	W	0h	If soft toggle is enabled set, this bit controls the toggle between values for those DACs that have been set in toggle mode 1 in the TOGGCONFIG register. Set to 1 to updated to Register B and clear to 0 for Register A.
5	AB-TOG0	W	0h	If soft toggle is enabled set, this bit controls the toggle between values for those DACs that have been set in toggle mode 0 in the TOGGCONFIG register. Set to 1 to update to Register B and clear to 0 for Register A.
4	LDAC	W	0h	Set this bit to 1 to synchronously load those DACs who have been set in synchronous mode in the SYNCCONFIG register.
3-0	SOFT-RESET[3:0]	W	0h	When set to the reserved code 1010 resets the device to its default state.

8.6.13 BRDCAST Register (Offset = 0Fh) [reset = 0000h]

BRDCAST is shown in Figure 8-18 and described in Table 8-21.

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Figure 8-18 BRDCAST Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
BRDCAST-DATA[15:0]
R/W-0h

Table 8-21 BRDCAST Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	BRDCAST-DATA[15:0]	R/W	0h	Writing to the BRDCAST register forces those DAC channels that have been set to broadcast in the BRDCONFIG register to update its data register data to the BRDCAST-DATA one. Data is MSB aligned in straight binary format and follows the format below: DAC81416: { DATA[15:0] } DAC71416: { DATA[13:0], x, x } DAC61416: { DATA[11:0], x, x, x, x} x – Don 't care bits

Bit

Field

Type

Reset

Description

15-0

BRDCAST-DATA[15:0]

R/W

0h

Writing to the BRDCAST register forces those DAC channels that have been set to broadcast in the BRDCONFIG register to update its data register data to the BRDCAST-DATA one.

Data is MSB aligned in straight binary format and follows the format below:

DAC81416: { DATA[15:0] }

DAC71416: { DATA[13:0], x, x }

DAC61416: { DATA[11:0], x, x, x, x}

x – Don 't care bits

8.6.14 DACn Register (Offset = 10h - 1Fh) [reset = 0000h]

DACn is shown in Figure 8-19 and described in Table 8-22.

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Figure 8-19 DACn Register

15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
DACn-DATA[15:0]
R/W-0h

Table 8-22 DACn Register Field Descriptions

Bit	Field	Type	Reset	Description
15-0	DACn-DATA[15:0]	R/W	0h	Stores the 16-, 14- or 12-bit data to be loaded to DACn in MSB aligned straight binary format. In differential DAC mode data is loaded into the lowest-valued DAC in the DAC pair (in pair DACxy, data is loaded into DACx and writes to DACy are ignored). Data follows the format below: DAC81416: { DATA[15:0] } DAC71416: { DATA[13:0], x, x } DAC61416: { DATA[11:0], x, x, x, x} x – Don 't care bits

Bit

Field

Type

Reset

Description

15-0

DACn-DATA[15:0]

R/W

0h

Stores the 16-, 14- or 12-bit data to be loaded to DACn in MSB aligned straight binary format. In differential DAC mode data is loaded into the lowest-valued DAC in the DAC pair (in pair DACxy, data is loaded into DACx and writes to DACy are ignored).

Data follows the format below:

DAC81416: { DATA[15:0] }

DAC71416: { DATA[13:0], x, x }

DAC61416: { DATA[11:0], x, x, x, x}

x – Don 't care bits

8.6.15 OFFSETn Register (Offset = 20h - 23h) [reset = 0000h]

OFFSETn is shown in Figure 8-20 and described in Table 8-23.

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Figure 8-20 OFFSETn Register

15	14	13	12	11	10	9	8
OFFSETab[7:0]
R/W-0h
7	6	5	4	3	2	1	0
OFFSETcd[7:0]
R/W-0h

Table 8-23 OFFSETn Register Field Descriptions

Bit	Field	Type	Reset	Description
15-8	OFFSETab[7:0]	R/W	0h	Provides offset adjustment to DACy in the differential DACx-y pair in two 's complement format. Data follows the format below: DAC81416: Format: { OFFSET[7:0] } Range: -128 LSB to +127 LSB DAC71416: Format: { OFFSET[5:0], x, x } Range: -32 LSB to +31 LSB DAC61416: Format: { OFFSET[3:0], x, x, x, x} Range: -8 LSB to +7 LSB x – Don 't care bits The differential DAC data register must be rewritten after updating the offset register. ab: 14-15, 10-11, 6-7 or 2-3; cd: 12-13, 8-9, 4-5 or 0-1
7-0	OFFSETcd[7:0]	R/W	0h

Bit

Field

Type

Reset

Description

15-8

OFFSETab[7:0]

R/W

0h

Provides offset adjustment to DACy in the differential DACx-y pair in two 's complement format.

Data follows the format below:

DAC81416:
- Format: { OFFSET[7:0] }
- Range: -128 LSB to +127 LSB
DAC71416:
- Format: { OFFSET[5:0], x, x }
- Range: -32 LSB to +31 LSB
DAC61416:
- Format: { OFFSET[3:0], x, x, x, x}
- Range: -8 LSB to +7 LSB

x – Don 't care bits

The differential DAC data register must be rewritten after updating the offset register.

ab: 14-15, 10-11, 6-7 or 2-3; cd: 12-13, 8-9, 4-5 or 0-1

7-0

OFFSETcd[7:0]

R/W

0h

Package Options

Mechanical Data (Package|Pins)

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8.6 Register Maps

8.6.1 NOP Register (Offset = 00h) [reset = 0000h]

8.6.2 DEVICEID Register (Offset = 01h) [reset = ----h]

8.6.3 STATUS Register (Offset = 02h) [reset = 0000h]

8.6.4 SPICONFIG Register (Offset = 03h) [reset = 0AA4h]

8.6.5 GENCONFIG Register (Offset = 04h) [reset = 7F00h]

8.6.6 BRDCONFIG Register (Offset = 05h) [reset = FFFFh]

8.6.7 SYNCCONFIG Register (Offset = 06h) [reset = 0000h]

8.6.8 TOGGCONFIG0 Register (Offset = 07h) [reset = 0000h]

8.6.9 TOGGCONFIG1 Register (Offset = 08h) [reset = 0000h]

8.6.10 DACPWDWN Register (Offset = 09h) [reset = FFFFh]

8.6.11 DACRANGEn Register (Offset = 0Ah - 0Dh) [reset = 0000h]

8.6.12 TRIGGER Register (Offset = 0Eh) [reset = 0000h]

8.6.13 BRDCAST Register (Offset = 0Fh) [reset = 0000h]

8.6.14 DACn Register (Offset = 10h - 1Fh) [reset = 0000h]

8.6.15 OFFSETn Register (Offset = 20h - 23h) [reset = 0000h]